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From: Jerin Jacob <jerinjacobk@gmail.com>
To: Thomas Monjalon <thomas@monjalon.net>
Cc: "Jerin Jacob" <jerinj@marvell.com>, dpdk-dev <dev@dpdk.org>,
	"Ferruh Yigit" <ferruh.yigit@intel.com>,
	"Ajit Khaparde" <ajit.khaparde@broadcom.com>,
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	tom@herbertland.com
Subject: Re: [dpdk-dev] [RFC PATCH 0/1] Dataplane Workload Accelerator library
Date: Wed, 20 Oct 2021 01:06:10 +0530	[thread overview]
Message-ID: <CALBAE1OnC=4w=adjVjGVEKRfefo77vjOM8eUmmxza6EzEOJM0A@mail.gmail.com> (raw)
In-Reply-To: <6870595.fqHcUuC4to@thomas>

On Wed, Oct 20, 2021 at 12:38 AM Thomas Monjalon <thomas@monjalon.net> wrote:
>
> 19/10/2021 20:14, jerinj@marvell.com:
> > Definition of Dataplane Workload Accelerator
> > --------------------------------------------
> > Dataplane Workload Accelerator(DWA) typically contains a set of CPUs,
> > Network controllers and programmable data acceleration engines for
> > packet processing, cryptography, regex engines, baseband processing, etc.
> > This allows DWA to offload  compute/packet processing/baseband/
> > cryptography-related workload from the host CPU to save the cost and power.
> > Also to enable scaling the workload by adding DWAs to the Host CPU as needed.
> >
> > Unlike other devices in DPDK, the DWA device is not fixed-function
> > due to the fact that it has CPUs and programmable HW accelerators.
> > This enables DWA personality/workload to be completely programmable.
> > Typical examples of DWA offloads are Flow/Session management,
> > Virtual switch, TLS offload, IPsec offload, l3fwd offload, etc.
>
> If I understand well, the idea is to abstract the offload
> of some stack layers in the hardware.

Yes. It may not just HW, For expressing the complicated workloads
may need CPU and/or other HW accelerators.

> I am not sure we should give an API for such stack layers in DPDK.

Why not?

> It looks to be the role of the dataplane application to finely manage
> how to use the hardware for a specific dataplane.

It is possible with this scheme.

> I believe the API for such layer would be either too big, or too limited,
> or not optimized for specific needs.

It will be optimized for specific needs as applications ask for what to do?
not how to do?

> If we really want to automate or abstract the HW/SW co-design,
> I think we should better look at compiler work like P4 or PANDA.

The compiler stuff is very static in nature. It can address the packet
transformation
workloads. Not the ones like IPsec or baseband offload.
Another way to look at it, GPU RFC started just because you are not able
to express all the workload in P4.

>
>

  reply	other threads:[~2021-10-19 19:36 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-19 18:14 jerinj
2021-10-19 18:14 ` [dpdk-dev] [RFC PATCH 1/1] dwa: introduce dataplane workload accelerator subsystem jerinj
2021-10-19 19:08 ` [dpdk-dev] [RFC PATCH 0/1] Dataplane Workload Accelerator library Thomas Monjalon
2021-10-19 19:36   ` Jerin Jacob [this message]
2021-10-19 20:42     ` Stephen Hemminger
2021-10-20  5:25       ` Jerin Jacob
2021-10-19 20:42     ` Tom Herbert
2021-10-20  5:38       ` Jerin Jacob
2021-10-22 12:00     ` Elena Agostini
2021-10-22 13:39       ` Jerin Jacob
2021-10-25  7:35 ` Mattias Rönnblom
2021-10-25  9:03   ` Jerin Jacob
2021-10-29 11:57     ` Mattias Rönnblom
2021-10-29 15:51       ` Jerin Jacob
2021-10-31  9:18         ` Mattias Rönnblom
2021-10-31 14:01           ` Jerin Jacob
2021-10-31 19:34             ` Thomas Monjalon
2021-10-31 21:13               ` Jerin Jacob
2021-10-31 21:55                 ` Thomas Monjalon
2021-10-31 22:19                   ` Jerin Jacob

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