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References: <20191127102222.31940-1-skori@marvell.com>
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From: Jerin Jacob <jerinjacobk@gmail.com>
Date: Tue, 17 Dec 2019 16:44:07 +0530
Message-ID: <CALBAE1Op+G5a+SUne4V+B4eq6+m0z9_APktZQkH8M5fkCma34A@mail.gmail.com>
To: "Gavin Hu (Arm Technology China)" <Gavin.Hu@arm.com>
Cc: Sunil Kumar Kori <skori@marvell.com>,
 "jerinj@marvell.com" <jerinj@marvell.com>, 
 Nithin Dabilpuram <ndabilpuram@marvell.com>,
 Vamsi Attunuru <vattunuru@marvell.com>, 
 "dev@dpdk.org" <dev@dpdk.org>, Harman Kalra <hkalra@marvell.com>, 
 Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>, nd <nd@arm.com>
Content-Type: text/plain; charset="UTF-8"
Subject: Re: [dpdk-dev] [PATCH v3 2/2] common/octeontx2: add polling based
 response mbox message
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> > +mbox_poll(struct otx2_mbox *mbox, uint32_t wait)
> > +{
> > +     uint32_t timeout = 0, sleep = 1;
> > +     uint64_t rsp_reg = 0;
> > +     uintptr_t reg_addr;
> > +
> > +     reg_addr = mbox->reg_base + mbox->intr_offset;
> > +     while (!rsp_reg) {
> The first iteration of (!rsp_reg) always evaluate to 'true'.
> Why not use do .. while to save one iteration?
> > +             rte_rmb();
> Rte_rmb is overkill, how is reg_addr mapped(what is the memory attribute? WC? cacheable? )
> If it is a PCI mmaped region, then rte_io_barrier is okay, I am proposing to relax the io barrier for aarch64 as a compiler barrier.
>  http://patches.dpdk.org/patch/61662/

It is the device memory and Linux kernel(_CPU_ not IO) is updating the
memory on the other side. I think,
we would need rte_smp_rmb() here. Since it was slow-path code, added
the full barrier here.
I think it is OK to change rte_smp_rmb() not to rte_io_* version. Correct?