* [dpdk-dev] [PATCH] common/cnxk: align npa stack to roc cache line size
@ 2021-08-30 13:52 Ashwin Sekhar T K
2021-09-16 14:27 ` Jerin Jacob
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Ashwin Sekhar T K @ 2021-08-30 13:52 UTC (permalink / raw)
To: dev; +Cc: jerinj, ndabilpuram, pbhagavatula, asekhar
NPA stack should be aligned to ROC cache line size.
Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations")
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
---
drivers/common/cnxk/roc_npa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
index d064d125c1..a0d2cc8f19 100644
--- a/drivers/common/cnxk/roc_npa.c
+++ b/drivers/common/cnxk/roc_npa.c
@@ -194,7 +194,7 @@ npa_stack_dma_alloc(struct npa_lf *lf, char *name, int pool_id, size_t size)
{
const char *mz_name = npa_stack_memzone_name(lf, pool_id, name);
- return plt_memzone_reserve_cache_align(mz_name, size);
+ return plt_memzone_reserve_aligned(mz_name, size, 0, ROC_ALIGN);
}
static inline int
--
2.32.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [dpdk-dev] [PATCH] common/cnxk: align npa stack to roc cache line size
2021-08-30 13:52 [dpdk-dev] [PATCH] common/cnxk: align npa stack to roc cache line size Ashwin Sekhar T K
@ 2021-09-16 14:27 ` Jerin Jacob
2021-09-16 15:15 ` Ferruh Yigit
2021-09-17 11:23 ` [dpdk-dev] [PATCH v2] common/cnxk: align NPA stack to ROC " Ashwin Sekhar T K
2 siblings, 0 replies; 6+ messages in thread
From: Jerin Jacob @ 2021-09-16 14:27 UTC (permalink / raw)
To: Ashwin Sekhar T K, Ferruh Yigit
Cc: dpdk-dev, Jerin Jacob, Nithin Dabilpuram, Pavan Nikhilesh
On Mon, Aug 30, 2021 at 7:23 PM Ashwin Sekhar T K <asekhar@marvell.com> wrote:
>
> NPA stack should be aligned to ROC cache line size.
>
> Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations")
>
> Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Applied to dpdk-next-net-mrvl/for-next-net. Thanks
> ---
> drivers/common/cnxk/roc_npa.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
> index d064d125c1..a0d2cc8f19 100644
> --- a/drivers/common/cnxk/roc_npa.c
> +++ b/drivers/common/cnxk/roc_npa.c
> @@ -194,7 +194,7 @@ npa_stack_dma_alloc(struct npa_lf *lf, char *name, int pool_id, size_t size)
> {
> const char *mz_name = npa_stack_memzone_name(lf, pool_id, name);
>
> - return plt_memzone_reserve_cache_align(mz_name, size);
> + return plt_memzone_reserve_aligned(mz_name, size, 0, ROC_ALIGN);
> }
>
> static inline int
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [dpdk-dev] [PATCH] common/cnxk: align npa stack to roc cache line size
2021-08-30 13:52 [dpdk-dev] [PATCH] common/cnxk: align npa stack to roc cache line size Ashwin Sekhar T K
2021-09-16 14:27 ` Jerin Jacob
@ 2021-09-16 15:15 ` Ferruh Yigit
2021-09-16 16:35 ` Jerin Jacob
2021-09-17 11:23 ` [dpdk-dev] [PATCH v2] common/cnxk: align NPA stack to ROC " Ashwin Sekhar T K
2 siblings, 1 reply; 6+ messages in thread
From: Ferruh Yigit @ 2021-09-16 15:15 UTC (permalink / raw)
To: Ashwin Sekhar T K, dev; +Cc: jerinj, ndabilpuram, pbhagavatula
On 8/30/2021 2:52 PM, Ashwin Sekhar T K wrote:
> NPA stack should be aligned to ROC cache line size.
>
Can you please document the long versions of 'NPA' & 'ROC' abbreviations?
Also for the patch title, since abbreviations needs to be uppercase, to automate
the check for these abbreviations, can you please add them to
'./devtools/words-case.txt' in separate patch.
And can you add some more context on the reasoning of the change, why it should
be aligned to cache line?
What is the impact user/application sees if it is not aligned, and after aligned?
Thanks,
ferruh
> Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations")
>
> Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
> ---
> drivers/common/cnxk/roc_npa.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
> index d064d125c1..a0d2cc8f19 100644
> --- a/drivers/common/cnxk/roc_npa.c
> +++ b/drivers/common/cnxk/roc_npa.c
> @@ -194,7 +194,7 @@ npa_stack_dma_alloc(struct npa_lf *lf, char *name, int pool_id, size_t size)
> {
> const char *mz_name = npa_stack_memzone_name(lf, pool_id, name);
>
> - return plt_memzone_reserve_cache_align(mz_name, size);
> + return plt_memzone_reserve_aligned(mz_name, size, 0, ROC_ALIGN);
> }
>
> static inline int
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [dpdk-dev] [PATCH] common/cnxk: align npa stack to roc cache line size
2021-09-16 15:15 ` Ferruh Yigit
@ 2021-09-16 16:35 ` Jerin Jacob
0 siblings, 0 replies; 6+ messages in thread
From: Jerin Jacob @ 2021-09-16 16:35 UTC (permalink / raw)
To: Ferruh Yigit
Cc: Ashwin Sekhar T K, dpdk-dev, Jerin Jacob, Nithin Dabilpuram,
Pavan Nikhilesh
On Thu, Sep 16, 2021 at 8:46 PM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>
> On 8/30/2021 2:52 PM, Ashwin Sekhar T K wrote:
> > NPA stack should be aligned to ROC cache line size.
> >
>
> Can you please document the long versions of 'NPA' & 'ROC' abbreviations?
>
> Also for the patch title, since abbreviations needs to be uppercase, to automate
> the check for these abbreviations, can you please add them to
> './devtools/words-case.txt' in separate patch.
Please do add NIX, NPC, CPT, SSO, LBK, MCAM too.
> And can you add some more context on the reasoning of the change, why it should
> be aligned to cache line?
> What is the impact user/application sees if it is not aligned, and after aligned?
>
> Thanks,
> ferruh
>
> > Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations")
> >
> > Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
> > ---
> > drivers/common/cnxk/roc_npa.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
> > index d064d125c1..a0d2cc8f19 100644
> > --- a/drivers/common/cnxk/roc_npa.c
> > +++ b/drivers/common/cnxk/roc_npa.c
> > @@ -194,7 +194,7 @@ npa_stack_dma_alloc(struct npa_lf *lf, char *name, int pool_id, size_t size)
> > {
> > const char *mz_name = npa_stack_memzone_name(lf, pool_id, name);
> >
> > - return plt_memzone_reserve_cache_align(mz_name, size);
> > + return plt_memzone_reserve_aligned(mz_name, size, 0, ROC_ALIGN);
> > }
> >
> > static inline int
> >
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [dpdk-dev] [PATCH v2] common/cnxk: align NPA stack to ROC cache line size
2021-08-30 13:52 [dpdk-dev] [PATCH] common/cnxk: align npa stack to roc cache line size Ashwin Sekhar T K
2021-09-16 14:27 ` Jerin Jacob
2021-09-16 15:15 ` Ferruh Yigit
@ 2021-09-17 11:23 ` Ashwin Sekhar T K
2021-09-21 9:12 ` Jerin Jacob
2 siblings, 1 reply; 6+ messages in thread
From: Ashwin Sekhar T K @ 2021-09-17 11:23 UTC (permalink / raw)
To: dev
Cc: jerinj, skori, skoteshwar, pbhagavatula, kirankumark, psatheesh,
asekhar, anoobj, gakhil, ferruh.yigit
Network Pool accelerator (NPA) is part of ROC (Rest Of Chip). So
NPA structures should be aligned to ROC Cache line size and not
CPU cache line size.
Non alignment of NPA stack to ROC cache line will result in
undefined runtime NPA behaviour.
Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations")
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
---
drivers/common/cnxk/roc_npa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
index d064d125c1..a0d2cc8f19 100644
--- a/drivers/common/cnxk/roc_npa.c
+++ b/drivers/common/cnxk/roc_npa.c
@@ -194,7 +194,7 @@ npa_stack_dma_alloc(struct npa_lf *lf, char *name, int pool_id, size_t size)
{
const char *mz_name = npa_stack_memzone_name(lf, pool_id, name);
- return plt_memzone_reserve_cache_align(mz_name, size);
+ return plt_memzone_reserve_aligned(mz_name, size, 0, ROC_ALIGN);
}
static inline int
--
2.32.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [dpdk-dev] [PATCH v2] common/cnxk: align NPA stack to ROC cache line size
2021-09-17 11:23 ` [dpdk-dev] [PATCH v2] common/cnxk: align NPA stack to ROC " Ashwin Sekhar T K
@ 2021-09-21 9:12 ` Jerin Jacob
0 siblings, 0 replies; 6+ messages in thread
From: Jerin Jacob @ 2021-09-21 9:12 UTC (permalink / raw)
To: Ashwin Sekhar T K, Ferruh Yigit
Cc: dpdk-dev, Jerin Jacob, Sunil Kumar Kori,
Satha Koteswara Rao Kottidi, Pavan Nikhilesh, Kiran Kumar K,
Satheesh Paul, Anoob Joseph, Akhil Goyal
On Fri, Sep 17, 2021 at 4:55 PM Ashwin Sekhar T K <asekhar@marvell.com> wrote:
>
> Network Pool accelerator (NPA) is part of ROC (Rest Of Chip). So
> NPA structures should be aligned to ROC Cache line size and not
> CPU cache line size.
>
> Non alignment of NPA stack to ROC cache line will result in
> undefined runtime NPA behaviour.
>
> Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations")
>
> Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
> Acked-by: Jerin Jacob <jerinj@marvell.com>
Applied to dpdk-next-net-mrvl/for-next-net. Thanks
> ---
> drivers/common/cnxk/roc_npa.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
> index d064d125c1..a0d2cc8f19 100644
> --- a/drivers/common/cnxk/roc_npa.c
> +++ b/drivers/common/cnxk/roc_npa.c
> @@ -194,7 +194,7 @@ npa_stack_dma_alloc(struct npa_lf *lf, char *name, int pool_id, size_t size)
> {
> const char *mz_name = npa_stack_memzone_name(lf, pool_id, name);
>
> - return plt_memzone_reserve_cache_align(mz_name, size);
> + return plt_memzone_reserve_aligned(mz_name, size, 0, ROC_ALIGN);
> }
>
> static inline int
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 6+ messages in thread
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2021-08-30 13:52 [dpdk-dev] [PATCH] common/cnxk: align npa stack to roc cache line size Ashwin Sekhar T K
2021-09-16 14:27 ` Jerin Jacob
2021-09-16 15:15 ` Ferruh Yigit
2021-09-16 16:35 ` Jerin Jacob
2021-09-17 11:23 ` [dpdk-dev] [PATCH v2] common/cnxk: align NPA stack to ROC " Ashwin Sekhar T K
2021-09-21 9:12 ` Jerin Jacob
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