From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5538AA0351; Mon, 17 Aug 2020 15:07:37 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 358941C0BC; Mon, 17 Aug 2020 15:07:36 +0200 (CEST) Received: from mail-io1-f65.google.com (mail-io1-f65.google.com [209.85.166.65]) by dpdk.org (Postfix) with ESMTP id 859A61BFF3 for ; Mon, 17 Aug 2020 15:07:34 +0200 (CEST) Received: by mail-io1-f65.google.com with SMTP id s189so17559422iod.2 for ; Mon, 17 Aug 2020 06:07:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=zOojer1NrgSUPZz9dincXbAqE+36NfiVa5+PTaTD0vw=; b=T/GNZNEerIa5RcKUvkbE2sNtRedA/rvnFsSpfNBSA2MidfatPwZrQSbC+xfqRBgy9a KLUk55qKK9+yRvpb/eMyQWuedh8wjtgwkvpNHplmZzK7Np+hAm3OeQD9z3B8vnSahPJe eTK7wtyxrAv454YjCEe4piVqx0GEM+GZfJ6NBG7heGgQabw7f4ozbnoHr5akosNywPi1 efyjoc8pY0o6+xzWSQen3eSmaruB3mOoaBwC8pc9zVj7mrBzEAR3e96gh5psLgZaoODJ lGRy4G2GJLJmvMV7ekpw7vrLYBvWVl/zAW3V6GB99B9JlBo9ljttzT972EfCtTsL78bS D/Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=zOojer1NrgSUPZz9dincXbAqE+36NfiVa5+PTaTD0vw=; b=opr4C0i1UZdbBbfggbVcnlp3StDuelj3JJf/B3I0FG1ZuWCGlaV+Za4C0pvoP6W4+O qjG0srVb3oz9WDwTmAIfIbv56N1oWsUf2gdQTn0sam8npyjsHuDfll0AVlDOFwBnG4bF 5RZt+uR7WoYYHuPCoODfINvJVwi1A9GK/6kRWx0hFZpQODfKLccLO2Wnmz4Ov+qE+IZR DxRqu04sTAsUbvqdIxvB+plh3WIya6tylcTqyH7G+Hdm3HkvAnKn6NW+7cBjEzH8R2Ig wQ4I6BPOtqARKRcVNr0NSlb09GmIa5VlNd3jyCPU+5yv4eEM87bVwWPq625a0XmRW26i BQfg== X-Gm-Message-State: AOAM532HeDOK818QGcT/W9FrtnwvZeOiknSJwKFqCDbRgp0bfR9QFgvt DK9O/5pqx/Z9lw+fcdtJ1sZHzhgS2+O4VFL09uKQgCQFqz0= X-Google-Smtp-Source: ABdhPJzHRFTPSqIiSuKgbHQqd/8jgRD/ionEUKxo/t+f1yiZ6lBTFze9TY2pC761IEvR7mH8MdMXwz8EiB7m+i75nVA= X-Received: by 2002:a02:a04d:: with SMTP id f13mr14569221jah.112.1597669653709; Mon, 17 Aug 2020 06:07:33 -0700 (PDT) MIME-Version: 1.0 References: <20200817124703.58157-1-huwei013@chinasoftinc.com> In-Reply-To: <20200817124703.58157-1-huwei013@chinasoftinc.com> From: Jerin Jacob Date: Mon, 17 Aug 2020 18:37:17 +0530 Message-ID: To: "Wei Hu (Xavier)" Cc: dpdk-dev , "Wei Hu (Xavier" , nd , Honnappa Nagarahalli , "Ruifeng Wang (Arm Technology China)" Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v2] lib/librte_eal: support SVE flag on ARM64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Mon, Aug 17, 2020 at 6:17 PM Wei Hu (Xavier) wrote: > > From: "Wei Hu (Xavier)" > > SVE is the next-generation SIMD extension of the ARMv8-A AArch64 > instruction set. > The related marco definition can be found in linux kernel: > arch/arm64/include/uapi/asm/hwcap.h > > This patch supports getting cpu SVE feature on ARM64 platform. > > Signed-off-by: Chengwen Feng > Signed-off-by: Wei Hu (Xavier) Change the git commit like eal/arm64: update CPU flags > --- > v1 -> v2: > Adds more sve-related definition to rte_cpu_feature_table, > sunch as SVE2, etc. > --- > lib/librte_eal/arm/include/rte_cpuflags_64.h | 1 + > lib/librte_eal/arm/rte_cpuflags.c | 11 +++++++++++ > 2 files changed, 12 insertions(+) > > diff --git a/lib/librte_eal/arm/include/rte_cpuflags_64.h b/lib/librte_eal/arm/include/rte_cpuflags_64.h > index 95cc01474..069844ddb 100644 > --- a/lib/librte_eal/arm/include/rte_cpuflags_64.h > +++ b/lib/librte_eal/arm/include/rte_cpuflags_64.h > @@ -22,6 +22,7 @@ enum rte_cpu_flag_t { > RTE_CPUFLAG_SHA2, > RTE_CPUFLAG_CRC32, > RTE_CPUFLAG_ATOMICS, > + RTE_CPUFLAG_SVE, Please intrdouce the flag for all newly added items as well. > RTE_CPUFLAG_AARCH64, > /* The last item */ > RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */ > diff --git a/lib/librte_eal/arm/rte_cpuflags.c b/lib/librte_eal/arm/rte_cpuflags.c > index caf3dc83a..97a9fcfd4 100644 > --- a/lib/librte_eal/arm/rte_cpuflags.c > +++ b/lib/librte_eal/arm/rte_cpuflags.c > @@ -95,6 +95,17 @@ const struct feature_entry rte_cpu_feature_table[] = { > FEAT_DEF(SHA2, REG_HWCAP, 6) > FEAT_DEF(CRC32, REG_HWCAP, 7) > FEAT_DEF(ATOMICS, REG_HWCAP, 8) > + FEAT_DEF(SVE, REG_HWCAP, 22) > + FEAT_DEF(SVE2, REG_HWCAP2, 1) > + FEAT_DEF(SVEAES, REG_HWCAP2, 2) > + FEAT_DEF(SVEPMULL, REG_HWCAP2, 3) > + FEAT_DEF(SVEBITPERM, REG_HWCAP2, 4) > + FEAT_DEF(SVESHA3, REG_HWCAP2, 5) > + FEAT_DEF(SVESM4, REG_HWCAP2, 6) Following stuff is missing HWCAP2_FLAGM2 (1 << 7) HWCAP2_FRINT (1 << 8) > + FEAT_DEF(SVEI8MM, REG_HWCAP2, 9) > + FEAT_DEF(SVEF32MM, REG_HWCAP2, 10) > + FEAT_DEF(SVEF64MM, REG_HWCAP2, 11) > + FEAT_DEF(SVEBF16, REG_HWCAP2, 12) > FEAT_DEF(AARCH64, REG_PLATFORM, 1) > }; > #endif /* RTE_ARCH */ > -- > 2.27.0 >