From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3B154A0547; Fri, 29 Oct 2021 16:17:09 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2222541143; Fri, 29 Oct 2021 16:17:09 +0200 (CEST) Received: from mail-il1-f177.google.com (mail-il1-f177.google.com [209.85.166.177]) by mails.dpdk.org (Postfix) with ESMTP id 26B584111F for ; Fri, 29 Oct 2021 16:17:08 +0200 (CEST) Received: by mail-il1-f177.google.com with SMTP id j28so4374279ila.1 for ; Fri, 29 Oct 2021 07:17:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=+aDM9oH0BK9pUkLjIEClvd/U9denHrREdgwXNCVfFW8=; b=BGZc8CdJBtKBn4vydJ6tc/bLdNqATNxEpQTo466pBU08KI8d5tBUIDCRnEQbJApGNW CMuV/naIbFw4+vCHpUUxZibhNGTy+VfV8xZrxH0nTfLdGoKN7kuYL8+/kz1Iv0T6fPm6 UzMdtKr/6dHtcu6LUz0oNHTu5+aoRckrlQOUB87wqPZMs0iq/oggY3vbUvd/NzRReg9x IfQx9cODw6QenrpHRi1K5B1+iK5ESgb3tS4SHz2J0hyQv66hhyChvSdjZ1ZM7swsyasm gUq0qI4ljrkn1VwO7HPmLJr2T5qz0UFRr9aMkSBzZryMQN+OGqSTviwz7XcZi9nO77Pl b7AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=+aDM9oH0BK9pUkLjIEClvd/U9denHrREdgwXNCVfFW8=; b=lxalofxiaX0xNGztxlFo5b0ro+Dh7gxA/7f5swlfecSBwDQWs8O9qvySkqnqu2eljW NNzBuQzfgca+OxFpInxd/sgtqdcinJ0mgEkeieCYVaXEY/YaPmibf5QngxqaNdHDDtJI BSAY6F/Ge7D89+gWDSUioGnSV93trfO9LMo64IPdVSz2tvSkZZYYKBKKdSN6rkHNVNvp fEjRhLbGou3NIShkpLWK0FG2cRwJ2gd/Y923oOYGQNy25eETTHqOzuoj30V1dEwmP1y/ bJWbZAB9S2eHZys9fNTKbgoBJ++q1KWK8LdBQi0CUgSHUOC+xAPgukqzIaJ/5EI427XO JOPw== X-Gm-Message-State: AOAM533y0AszdTG2s/zgP7ANc0jv+p9VPV3BQV3EKylu1e452Jgoglai yileuwHicl/4AJwVRqQJC6HQwQsd9chyFWIzpOc= X-Google-Smtp-Source: ABdhPJzNSL1IZWLC8+3wCM2yVqNbwkX6wHgt3hk7sZEBAs9dyOZuY4JbKPC2r+dlvoob3fhMWiYAT9WgModJ0eBVOYo= X-Received: by 2002:a05:6e02:1bcb:: with SMTP id x11mr5348091ilv.94.1635517027085; Fri, 29 Oct 2021 07:17:07 -0700 (PDT) MIME-Version: 1.0 References: <20211026153933.15467-1-pnalla@marvell.com> In-Reply-To: <20211026153933.15467-1-pnalla@marvell.com> From: Jerin Jacob Date: Fri, 29 Oct 2021 19:46:38 +0530 Message-ID: To: Pradeep Nalla Cc: Radha Mohan Chintakuntla , Veerasenareddy Burru , Jerin Jacob , Satananda Burla , dpdk-dev Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH] net/octeontx_ep: Remove otx2 common dependency X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Tue, Oct 26, 2021 at 9:10 PM Pradeep Nalla wrote: > > octeontx_ep driver's dependency on octeontx2 common code is > removed as going forward ep driver will include files from > its own path. > > Signed-off-by: Pradeep Nalla Updated as net/octeontx_ep: remove octeontx2 dependency octeontx_ep driver's dependency on octeontx2 common code is removed as going forward ep driver will include files from its own path. Signed-off-by: Pradeep Nalla Acked-by: Jerin Jacob Applied to dpdk-next-net-mrvl/for-next-net. Thanks > --- > drivers/net/octeontx_ep/meson.build | 2 - > drivers/net/octeontx_ep/otx2_ep_vf.c | 13 +-- > drivers/net/octeontx_ep/otx2_ep_vf.h | 112 ++++++++++++++++++++++++ > drivers/net/octeontx_ep/otx_ep_common.h | 3 + > drivers/net/octeontx_ep/otx_ep_ethdev.c | 1 - > 5 files changed, 122 insertions(+), 9 deletions(-) > > diff --git a/drivers/net/octeontx_ep/meson.build b/drivers/net/octeontx_ep/meson.build > index 89f88caff0..b15646b82a 100644 > --- a/drivers/net/octeontx_ep/meson.build > +++ b/drivers/net/octeontx_ep/meson.build > @@ -2,7 +2,6 @@ > # Copyright(C) 2021 Marvell. > # > > -deps += ['common_octeontx2'] > sources = files( > 'otx_ep_ethdev.c', > 'otx_ep_rxtx.c', > @@ -10,4 +9,3 @@ sources = files( > 'otx2_ep_vf.c', > ) > > -includes += include_directories('../../common/octeontx2') > diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.c b/drivers/net/octeontx_ep/otx2_ep_vf.c > index 64cd8731d3..0716beb9b1 100644 > --- a/drivers/net/octeontx_ep/otx2_ep_vf.c > +++ b/drivers/net/octeontx_ep/otx2_ep_vf.c > @@ -2,7 +2,8 @@ > * Copyright(C) 2021 Marvell. > */ > > -#include "otx2_common.h" > +#include > +#include > #include "otx_ep_common.h" > #include "otx2_ep_vf.h" > > @@ -215,7 +216,7 @@ otx2_vf_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no) > > otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no)); > > - otx2_info("IQ[%d] enable done", q_no); > + otx_ep_info("IQ[%d] enable done", q_no); > > return 0; > } > @@ -229,7 +230,7 @@ otx2_vf_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no) > reg_val |= 0x1ull; > otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no)); > > - otx2_info("OQ[%d] enable done", q_no); > + otx_ep_info("OQ[%d] enable done", q_no); > > return 0; > } > @@ -326,10 +327,10 @@ otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep) > if (otx_ep->conf == NULL) { > otx_ep->conf = otx2_ep_get_defconf(otx_ep); > if (otx_ep->conf == NULL) { > - otx2_err("SDP VF default config not found"); > + otx_ep_err("SDP VF default config not found"); > return -ENOENT; > } > - otx2_info("Default config is used"); > + otx_ep_info("Default config is used"); > } > > /* Get IOQs (RPVF] count */ > @@ -338,7 +339,7 @@ otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep) > otx_ep->sriov_info.rings_per_vf = ((reg_val >> SDP_VF_R_IN_CTL_RPVF_POS) > & SDP_VF_R_IN_CTL_RPVF_MASK); > > - otx2_info("SDP RPVF: %d", otx_ep->sriov_info.rings_per_vf); > + otx_ep_info("SDP RPVF: %d", otx_ep->sriov_info.rings_per_vf); > > otx_ep->fn_list.setup_iq_regs = otx2_vf_setup_iq_regs; > otx_ep->fn_list.setup_oq_regs = otx2_vf_setup_oq_regs; > diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.h b/drivers/net/octeontx_ep/otx2_ep_vf.h > index 5e5aefbc1c..9326925025 100644 > --- a/drivers/net/octeontx_ep/otx2_ep_vf.h > +++ b/drivers/net/octeontx_ep/otx2_ep_vf.h > @@ -4,6 +4,118 @@ > #ifndef _OTX2_EP_VF_H_ > #define _OTX2_EP_VF_H_ > > +#include > + > +#define SDP_VF_R_IN_CTL_IDLE (0x1ull << 28) > +#define SDP_VF_R_IN_CTL_RDSIZE (0x3ull << 25) /* Setting to max(4) */ > +#define SDP_VF_R_IN_CTL_IS_64B (0x1ull << 24) > +#define SDP_VF_R_IN_CTL_ESR (0x1ull << 1) > + > +#define SDP_VF_BUSY_LOOP_COUNT (10000) > + > +/* SDP VF OQ Masks */ > +#define SDP_VF_R_OUT_CTL_IDLE (1ull << 40) > +#define SDP_VF_R_OUT_CTL_ES_I (1ull << 34) > +#define SDP_VF_R_OUT_CTL_NSR_I (1ull << 33) > +#define SDP_VF_R_OUT_CTL_ROR_I (1ull << 32) > +#define SDP_VF_R_OUT_CTL_ES_D (1ull << 30) > +#define SDP_VF_R_OUT_CTL_NSR_D (1ull << 29) > +#define SDP_VF_R_OUT_CTL_ROR_D (1ull << 28) > +#define SDP_VF_R_OUT_CTL_ES_P (1ull << 26) > +#define SDP_VF_R_OUT_CTL_NSR_P (1ull << 25) > +#define SDP_VF_R_OUT_CTL_ROR_P (1ull << 24) > +#define SDP_VF_R_OUT_CTL_IMODE (1ull << 23) > + > +/* SDP VF Register definitions */ > +#define SDP_VF_RING_OFFSET (0x1ull << 17) > + > +/* SDP VF IQ Registers */ > +#define SDP_VF_R_IN_CONTROL_START (0x10000) > +#define SDP_VF_R_IN_ENABLE_START (0x10010) > +#define SDP_VF_R_IN_INSTR_BADDR_START (0x10020) > +#define SDP_VF_R_IN_INSTR_RSIZE_START (0x10030) > +#define SDP_VF_R_IN_INSTR_DBELL_START (0x10040) > +#define SDP_VF_R_IN_CNTS_START (0x10050) > +#define SDP_VF_R_IN_INT_LEVELS_START (0x10060) > +#define SDP_VF_R_IN_PKT_CNT_START (0x10080) > +#define SDP_VF_R_IN_BYTE_CNT_START (0x10090) > + > +#define SDP_VF_R_IN_CONTROL(ring) \ > + (SDP_VF_R_IN_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +#define SDP_VF_R_IN_ENABLE(ring) \ > + (SDP_VF_R_IN_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +#define SDP_VF_R_IN_INSTR_BADDR(ring) \ > + (SDP_VF_R_IN_INSTR_BADDR_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +#define SDP_VF_R_IN_INSTR_RSIZE(ring) \ > + (SDP_VF_R_IN_INSTR_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +#define SDP_VF_R_IN_INSTR_DBELL(ring) \ > + (SDP_VF_R_IN_INSTR_DBELL_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +#define SDP_VF_R_IN_CNTS(ring) \ > + (SDP_VF_R_IN_CNTS_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +#define SDP_VF_R_IN_INT_LEVELS(ring) \ > + (SDP_VF_R_IN_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +#define SDP_VF_R_IN_PKT_CNT(ring) \ > + (SDP_VF_R_IN_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +#define SDP_VF_R_IN_BYTE_CNT(ring) \ > + (SDP_VF_R_IN_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +/* SDP VF OQ Registers */ > +#define SDP_VF_R_OUT_CNTS_START (0x10100) > +#define SDP_VF_R_OUT_INT_LEVELS_START (0x10110) > +#define SDP_VF_R_OUT_SLIST_BADDR_START (0x10120) > +#define SDP_VF_R_OUT_SLIST_RSIZE_START (0x10130) > +#define SDP_VF_R_OUT_SLIST_DBELL_START (0x10140) > +#define SDP_VF_R_OUT_CONTROL_START (0x10150) > +#define SDP_VF_R_OUT_ENABLE_START (0x10160) > +#define SDP_VF_R_OUT_PKT_CNT_START (0x10180) > +#define SDP_VF_R_OUT_BYTE_CNT_START (0x10190) > + > +#define SDP_VF_R_OUT_CONTROL(ring) \ > + (SDP_VF_R_OUT_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +#define SDP_VF_R_OUT_ENABLE(ring) \ > + (SDP_VF_R_OUT_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +#define SDP_VF_R_OUT_SLIST_BADDR(ring) \ > + (SDP_VF_R_OUT_SLIST_BADDR_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +#define SDP_VF_R_OUT_SLIST_RSIZE(ring) \ > + (SDP_VF_R_OUT_SLIST_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +#define SDP_VF_R_OUT_SLIST_DBELL(ring) \ > + (SDP_VF_R_OUT_SLIST_DBELL_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +#define SDP_VF_R_OUT_CNTS(ring) \ > + (SDP_VF_R_OUT_CNTS_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +#define SDP_VF_R_OUT_INT_LEVELS(ring) \ > + (SDP_VF_R_OUT_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +#define SDP_VF_R_OUT_PKT_CNT(ring) \ > + (SDP_VF_R_OUT_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +#define SDP_VF_R_OUT_BYTE_CNT(ring) \ > + (SDP_VF_R_OUT_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET)) > + > +/* SDP VF IQ Masks */ > +#define SDP_VF_R_IN_CTL_RPVF_MASK (0xF) > +#define SDP_VF_R_IN_CTL_RPVF_POS (48) > + > +/* IO Access */ > +#define otx2_read64(addr) rte_read64_relaxed((void *)(addr)) > +#define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr)) > + > +#define PCI_DEVID_OCTEONTX2_EP_NET_VF 0xB203 /* OCTEON TX2 EP mode */ > +#define PCI_DEVID_CN98XX_EP_NET_VF 0xB103 > + > int > otx2_ep_vf_setup_device(struct otx_ep_device *sdpvf); > > diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h > index 5d0b30a1f0..fd5e8ed263 100644 > --- a/drivers/net/octeontx_ep/otx_ep_common.h > +++ b/drivers/net/octeontx_ep/otx_ep_common.h > @@ -504,5 +504,8 @@ struct otx_ep_buf_free_info { > #define OTX_EP_CLEAR_SLIST_DBELL 0xFFFFFFFF > #define OTX_EP_CLEAR_SDP_OUT_PKT_CNT 0xFFFFFFFFF > > +/* PCI IDs */ > +#define PCI_VENDOR_ID_CAVIUM 0x177D > + > extern int otx_net_ep_logtype; > #endif /* _OTX_EP_COMMON_H_ */ > diff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c > index 698d22e226..5e371595a5 100644 > --- a/drivers/net/octeontx_ep/otx_ep_ethdev.c > +++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c > @@ -4,7 +4,6 @@ > > #include > > -#include "otx2_common.h" > #include "otx_ep_common.h" > #include "otx_ep_vf.h" > #include "otx2_ep_vf.h" > -- > 2.17.1 >