From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6F3CAA0579; Thu, 8 Apr 2021 10:59:56 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 520AB141137; Thu, 8 Apr 2021 10:59:56 +0200 (CEST) Received: from mail-io1-f46.google.com (mail-io1-f46.google.com [209.85.166.46]) by mails.dpdk.org (Postfix) with ESMTP id 77381141136 for ; Thu, 8 Apr 2021 10:59:54 +0200 (CEST) Received: by mail-io1-f46.google.com with SMTP id b10so1438776iot.4 for ; Thu, 08 Apr 2021 01:59:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Vd1oGqpv7up4qonivlRN28BGd1oYCUCR67FUr2Z/iXg=; b=IGApAbtfiup4D/4ux4h+wGkR6RUKq731C4JGoS9fnE0ZIXaia39qiOtr8VbJz3JzEC q8H7nWskj3wbGk378fVAhzL4MdpV5DGvPtgPFLYGSXZIe+MnchlWI0ZzpAUcVZqZjaRF PLcIM6rVFNvZrOECXftsygZv3F5at+bRhpVMfdAF8w9sJVJOn1pvQRE6XoGP+Pg9CcKM +OEtqtCVS0CGdnAB81+9OYEMJ57V83Cm+fOzDn6fHj/FVCIISF9QFVzStXdMbNZOBoHg 8eWLwhFfcACdnCQOLjzfVPf38lhewPEvtYAG64vX4V7NeKWPMWTVlpuoTufJjPwb3dPk btRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Vd1oGqpv7up4qonivlRN28BGd1oYCUCR67FUr2Z/iXg=; b=Ej5zk1lfFyPNl7YZfvc1tMTnbObk+/dI0HIHakVpkxi5r1N49WSzlcj5QAgr5UHGhO WUcqkvNSyMTkAaJbCf++xxAea/Q9SICxNwowLD0nAF3Cv4uaF9faG4zAQv1iVR5W0FnZ THemP3Xl7kmZi1mjYmdgh3mcGOMguaCAaIu/HgWap2pzN9q/KzOuERpiGnUU00k9RGvh noN5WRZNfetXg4vVifos9JLeTLtt6RPPsuAmwfDo1KmiDtU4X/EgJmpTwXnYFi7KL1cn H7FdWg32TXrEq2WSsda8djD7p59J9mAQMQNDDPpWQEaMdJ3z8yXCPPaif4jBzNzNNg96 7Ycw== X-Gm-Message-State: AOAM533D2oWUfFEX8b9gRpiQWgiJh92ReDvBPpNsJeFhi6etRnr8K7fT EFKNbgemO0tbhd6u25I8QXZY36UXLJ7Be1yo3cI= X-Google-Smtp-Source: ABdhPJx5UWNAKhTm6WHdufqVYIH4ub+Q7h9H7kRPMYwcfe9q3xtURIsLcbBcytTU5CaDyFbUtzFSXgbXoLcS2YAwmLw= X-Received: by 2002:a6b:b7cd:: with SMTP id h196mr5858324iof.59.1617872393897; Thu, 08 Apr 2021 01:59:53 -0700 (PDT) MIME-Version: 1.0 References: <20210305162149.2196166-1-asekhar@marvell.com> <20210406151115.1889455-1-asekhar@marvell.com> In-Reply-To: <20210406151115.1889455-1-asekhar@marvell.com> From: Jerin Jacob Date: Thu, 8 Apr 2021 14:29:37 +0530 Message-ID: To: Ashwin Sekhar T K Cc: dpdk-dev , Jerin Jacob , Sunil Kumar Kori , Satha Koteswara Rao Kottidi , Pavan Nikhilesh , Kiran Kumar K , Satheesh Paul Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v3 00/11] Add Marvell CNXK mempool driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Tue, Apr 6, 2021 at 8:41 PM Ashwin Sekhar T K wrote: > > This patchset adds the mempool/cnxk driver which provides the support for the > integrated mempool device found in Marvell CN10K SoC. > > The code includes mempool driver functionality for Marvell CN9K SoC as well, > but right now it is not enabled. The future plan is to deprecate existing > mempool/octeontx2 driver once the 'CNXK' drivers are feature complete for > Marvell CN9K SoC. > > Depends-on: series-16131 ("Add Marvell CNXK common driver") > > v3: > - Change batch op data initialization to plt init callback. > - Reserve a memzone for batch op data. > - Handle batch op data initialization in secondary process. 1) http://patches.dpdk.org/project/dpdk/patch/20210406151115.1889455-12-asekhar@marvell.com/ shows some CI issues, Could you check, Is this valid or not? 2) Common code series has added the following [1] section, Could you add mempool driver update as the second bullet. Rest looks good to me. [1] diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index 2ffeb92..cc6e53e 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -65,6 +65,15 @@ New Features representor=[[c#]pf#]sf# sf[0,2-1023] /* 1023 SFs. */ representor=[c#]pf# c2pf[0,1] /* 2 PFs on controller 2. */ +* **Added support for Marvell CN10K SoC drivers.** + + Added Marvell CN10K SoC support. Marvell CN10K SoC are based on Octeon 10 + family of ARM64 processors with ARM Neoverse N2 core with accelerators for + packet processing, timers, cryptography, etc. + + * Added common/cnxk driver consisting of common API to be used by + net, crypto and event PMD's. > > Ashwin Sekhar T K (11): > mempool/cnxk: add build infra and doc > mempool/cnxk: add device probe/remove > mempool/cnxk: add generic ops > mempool/cnxk: register plt init callback > mempool/cnxk: add cn9k mempool ops > mempool/cnxk: add cn9k optimized mempool enqueue/dequeue > mempool/cnxk: add cn10k mempool ops > mempool/cnxk: add batch op init > mempool/cnxk: add cn10k batch enqueue op > mempool/cnxk: add cn10k get count op > mempool/cnxk: add cn10k batch dequeue op > > MAINTAINERS | 6 + > doc/guides/mempool/cnxk.rst | 91 +++++++ > doc/guides/mempool/index.rst | 1 + > doc/guides/platform/cnxk.rst | 3 + > drivers/mempool/cnxk/cn10k_mempool_ops.c | 319 +++++++++++++++++++++++ > drivers/mempool/cnxk/cn9k_mempool_ops.c | 89 +++++++ > drivers/mempool/cnxk/cnxk_mempool.c | 202 ++++++++++++++ > drivers/mempool/cnxk/cnxk_mempool.h | 28 ++ > drivers/mempool/cnxk/cnxk_mempool_ops.c | 191 ++++++++++++++ > drivers/mempool/cnxk/meson.build | 16 ++ > drivers/mempool/cnxk/version.map | 3 + > drivers/mempool/meson.build | 3 +- > 12 files changed, 951 insertions(+), 1 deletion(-) > create mode 100644 doc/guides/mempool/cnxk.rst > create mode 100644 drivers/mempool/cnxk/cn10k_mempool_ops.c > create mode 100644 drivers/mempool/cnxk/cn9k_mempool_ops.c > create mode 100644 drivers/mempool/cnxk/cnxk_mempool.c > create mode 100644 drivers/mempool/cnxk/cnxk_mempool.h > create mode 100644 drivers/mempool/cnxk/cnxk_mempool_ops.c > create mode 100644 drivers/mempool/cnxk/meson.build > create mode 100644 drivers/mempool/cnxk/version.map > > -- > 2.31.0 >