From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5DB54A04A6; Mon, 24 Jan 2022 10:06:41 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4153740E2D; Mon, 24 Jan 2022 10:06:41 +0100 (CET) Received: from mail-io1-f44.google.com (mail-io1-f44.google.com [209.85.166.44]) by mails.dpdk.org (Postfix) with ESMTP id 85AB440040 for ; Mon, 24 Jan 2022 10:06:40 +0100 (CET) Received: by mail-io1-f44.google.com with SMTP id h23so18549345iol.11 for ; Mon, 24 Jan 2022 01:06:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=E6+UxOL8FTGvP/7/qkiu56Q9iJQb81Ejbnrd0R9p06o=; b=AmbB+mvmqnbwj4y05nro0nhVKvrvnvmjK0qRKhaX1G8gjEk4SjdYSaZpxJIlnRJTX4 bnuj3RJK6bXCsu+BRVRcXj/858B41ZHKLT/xgWjQInzNOmDQAujdURpI3WNcJoDu8skC mpfxZMYpj+p1ta+1B/K6csHblyt7vlw1YUbWK7YUIk4DuD5AAxNnNFlqNnFfzKNkqpAP UdQ8swElgkyk9a6zOp0DgH8baOQeGTxfW1Sg076y0R4Iz9hU4p6hBV4N8YsTjfDk1NXU DirQEsLOeY/n3S3hZk6Yl+iJLRh0U0EH6Uwj9qx5bIfVotLGmhP3BvY7uBs9JsbOFsrX sDhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=E6+UxOL8FTGvP/7/qkiu56Q9iJQb81Ejbnrd0R9p06o=; b=0/iR4v2aeuhr2yVd+f3+OEsBbcyQFdc9QY3RNZOKPhAnFJ4IcCQRZh1092I1+Xwjv5 gMp2qnM8G53TAxyLRVyjbL0kklDG+vvuK8Z220jyz5y8AIZqka2y6ERWbrHoukdWUSAC z9I4aHItdLVM5lTlyWtP5thOv0B3NFJpkWngWGhqyNVGlThXOJKg0JUsqtWBlJcXhdPi Vw17jCAqNvLrAE/oqUBjXCNEcpw8O3t/7irG63kPfn+ae3BSSwi0cRe275fIVT70DHG9 h/3Zp08WvcvMWB7ffbDrLt0Ai9XHr5WhbQ8yyonZmezNzwzonPW4a4SOeBNu5kT375Mb 3D0Q== X-Gm-Message-State: AOAM532buBF41/MmWFo04Y2UUeR+nG/m6xN3R0pRLodcdq8dC5JmDyw0 pEqJjBgzbA2KrH5bvu8sEFZ1Viqwn56N48Ceiz4= X-Google-Smtp-Source: ABdhPJzdg/653wovJcPUvcrFpx5rtWuEb/2otToTtiPV4r+HgG26ge7NypfphK1bc6rFpAanNB7x06y6iWMOmF/kk2Q= X-Received: by 2002:a02:7114:: with SMTP id n20mr3895288jac.158.1643015199754; Mon, 24 Jan 2022 01:06:39 -0800 (PST) MIME-Version: 1.0 References: <20211213205424.5588-1-pbhagavatula@marvell.com> In-Reply-To: <20211213205424.5588-1-pbhagavatula@marvell.com> From: Jerin Jacob Date: Mon, 24 Jan 2022 14:36:13 +0530 Message-ID: Subject: Re: [PATCH] common/cnxk: add workaround for vWQE flush To: Pavan Nikhilesh Cc: Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , dpdk-dev Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Tue, Dec 14, 2021 at 2:24 AM wrote: > > From: Pavan Nikhilesh > > Due to an errata writing to vWQE flush register might hang NIX. > Add workaround for vWQE flush hang by waiting for the max > coalescing timeout to flush out any pending vWQEs. Fixes: ee48f711f3b0 ("common/cnxk: support NIX inline inbound and outbound setup") Cc: stable@dpdk.org > > Signed-off-by: Pavan Nikhilesh Acked-by: Jerin Jacob Applied to dpdk-next-net-eventdev/for-main. Thanks > --- > drivers/common/cnxk/roc_nix_inl.c | 3 +-- > drivers/common/cnxk/roc_nix_inl_dev.c | 12 ++++++++++++ > drivers/common/cnxk/roc_nix_inl_priv.h | 1 + > drivers/common/cnxk/roc_nix_priv.h | 1 + > drivers/common/cnxk/roc_nix_queue.c | 19 +++++++++++++++++-- > 5 files changed, 32 insertions(+), 4 deletions(-) > > diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c > index f0fc690417..e8981c4aa4 100644 > --- a/drivers/common/cnxk/roc_nix_inl.c > +++ b/drivers/common/cnxk/roc_nix_inl.c > @@ -595,8 +595,7 @@ roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq) > plt_err("Failed to disable inline device rq, rc=%d", rc); > > /* Flush NIX LF for CN10K */ > - if (roc_model_is_cn10k()) > - plt_write64(0, inl_dev->nix_base + NIX_LF_OP_VWQE_FLUSH); > + nix_rq_vwqe_flush(rq, inl_dev->vwqe_interval); > > return rc; > } > diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c > index a0fe6ecd82..10912a6c93 100644 > --- a/drivers/common/cnxk/roc_nix_inl_dev.c > +++ b/drivers/common/cnxk/roc_nix_inl_dev.c > @@ -346,6 +346,7 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev) > struct mbox *mbox = dev->mbox; > struct nix_lf_alloc_rsp *rsp; > struct nix_lf_alloc_req *req; > + struct nix_hw_info *hw_info; > size_t inb_sa_sz; > int i, rc = -ENOSPC; > void *sa; > @@ -382,6 +383,17 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev) > inl_dev->qints = rsp->qints; > inl_dev->cints = rsp->cints; > > + /* Get VWQE info if supported */ > + if (roc_model_is_cn10k()) { > + mbox_alloc_msg_nix_get_hw_info(mbox); > + rc = mbox_process_msg(mbox, (void *)&hw_info); > + if (rc) { > + plt_err("Failed to get HW info, rc=%d", rc); > + goto lf_free; > + } > + inl_dev->vwqe_interval = hw_info->vwqe_delay; > + } > + > /* Register nix interrupts */ > rc = nix_inl_nix_register_irqs(inl_dev); > if (rc) { > diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h > index 3dc526f929..be53a3fa81 100644 > --- a/drivers/common/cnxk/roc_nix_inl_priv.h > +++ b/drivers/common/cnxk/roc_nix_inl_priv.h > @@ -35,6 +35,7 @@ struct nix_inl_dev { > /* NIX data */ > uint8_t lf_tx_stats; > uint8_t lf_rx_stats; > + uint16_t vwqe_interval; > uint16_t cints; > uint16_t qints; > struct roc_nix_rq rq; > diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h > index 04575af295..deb2a6ba11 100644 > --- a/drivers/common/cnxk/roc_nix_priv.h > +++ b/drivers/common/cnxk/roc_nix_priv.h > @@ -377,6 +377,7 @@ int nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg, > int nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable); > int nix_tm_bp_config_get(struct roc_nix *roc_nix, bool *is_enabled); > int nix_tm_bp_config_set(struct roc_nix *roc_nix, bool enable); > +void nix_rq_vwqe_flush(struct roc_nix_rq *rq, uint16_t vwqe_interval); > > /* > * TM priv utils. > diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c > index c8c8401d81..d5f6813e69 100644 > --- a/drivers/common/cnxk/roc_nix_queue.c > +++ b/drivers/common/cnxk/roc_nix_queue.c > @@ -28,6 +28,22 @@ nix_qsize_clampup(uint32_t val) > return i; > } > > +void > +nix_rq_vwqe_flush(struct roc_nix_rq *rq, uint16_t vwqe_interval) > +{ > + uint64_t wait_ns; > + > + if (!roc_model_is_cn10k()) > + return; > + /* Due to HW errata writes to VWQE_FLUSH might hang, so instead > + * wait for max vwqe timeout interval. > + */ > + if (rq->vwqe_ena) { > + wait_ns = rq->vwqe_wait_tmo * (vwqe_interval + 1) * 100; > + plt_delay_us((wait_ns / 1E3) + 1); > + } > +} > + > int > nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable) > { > @@ -66,9 +82,8 @@ roc_nix_rq_ena_dis(struct roc_nix_rq *rq, bool enable) > int rc; > > rc = nix_rq_ena_dis(&nix->dev, rq, enable); > + nix_rq_vwqe_flush(rq, nix->vwqe_interval); > > - if (roc_model_is_cn10k()) > - plt_write64(rq->qid, nix->base + NIX_LF_OP_VWQE_FLUSH); > return rc; > } > > -- > 2.17.1 >