From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 09CE442CC4; Thu, 15 Jun 2023 10:51:13 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DD7EB40DDA; Thu, 15 Jun 2023 10:51:12 +0200 (CEST) Received: from mail-vs1-f47.google.com (mail-vs1-f47.google.com [209.85.217.47]) by mails.dpdk.org (Postfix) with ESMTP id 103BD40A84 for ; Thu, 15 Jun 2023 10:51:12 +0200 (CEST) Received: by mail-vs1-f47.google.com with SMTP id ada2fe7eead31-43f44f5f8f2so655248137.0 for ; Thu, 15 Jun 2023 01:51:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686819071; x=1689411071; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=x9qEms6bFZMXVaNTGNonR//7WloXcEA7+p7KTLaTCE4=; b=JQK3eUPkXA+RDXAMU7iQXcaD3VNldnG0owxsjuLwlc8PNAnRvGAnp5IGS4+455bAAp f7wvGSsWyoYcpKNRzTNfxJrgm0Iy8VSWYYL1XY9IuUCiXTv8PxYQ6HzlpQRIx6bjEzVG kXDBbDm0z1GphnD2GksfoMGn6ZCHft0YP6vlNniZqIzoLWDiTljOQ0HPjuM9qUmaQStz wcmtjmTurwNKPX/QH1nY1ZeR6+HmAgyR+qPqJ8e5oWzU/GqcfMHiRsEphe69GVC/5AWl 24bvRIGONAWImvuhy3l7fhHAx9yWRF968BDjwS9O5vROxmCvmJWe2iiYRihfg4/+u82g l5jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686819071; x=1689411071; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x9qEms6bFZMXVaNTGNonR//7WloXcEA7+p7KTLaTCE4=; b=jg87NVC0aHHj274B85FMsJtDdjtbOqWPNHiuvztP7cNeUIGjPWOhLiypGdYS+uTw7d 0x6qNM7unFIxjZfHYfwm8rZmArhNViSDnACtYqIWJSzvUv0BusssvlxPVwLuD8QAMI6n TKuNIPlE8tADJVZlh5oqDBu+meEirhlu0RnbY0ZaBLa6E03LP39zqCZW5uStuT6Xqt5j +lcMln9l0qdvY4jvbJPHu76r76V9RVmb29v0TnWbSWZ5N7TyiLzgtzTAFZRqSbE2aaac RI7owl6XngjN7Lgyr5pScb6jlj6UyFjg4ogyFyopwkyrxvsyj0Lmf8M4oeIfZ0y/tsON xs/A== X-Gm-Message-State: AC+VfDx/W92ZguNwMZ3/mf+Ic7QLhJJMCvozSHJduOTHY4LP5ZmGAyXx T5L9GS1oKVgJNdgp4Auys3e9TDIf7kx5RLpHDpk/MZ+JEq1N0A== X-Google-Smtp-Source: ACHHUZ5T29VWaVgs6OlyE1vCTOFQgMhc1JZt+9L2qW6oYv60xyk/s0MpV/dcKGuEUrOJ5y7HHtDFuoOmkbJnpWn/b2w= X-Received: by 2002:a1f:4588:0:b0:46e:8a0e:2609 with SMTP id s130-20020a1f4588000000b0046e8a0e2609mr1885863vka.5.1686819071293; Thu, 15 Jun 2023 01:51:11 -0700 (PDT) MIME-Version: 1.0 References: <1686805463-19231-1-git-send-email-skoteshwar@marvell.com> In-Reply-To: <1686805463-19231-1-git-send-email-skoteshwar@marvell.com> From: Jerin Jacob Date: Thu, 15 Jun 2023 14:20:45 +0530 Message-ID: Subject: Re: [PATCH] net/cnxk: flush SQ before configuring MTU To: skoteshwar@marvell.com Cc: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , dev@dpdk.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Thu, Jun 15, 2023 at 10:34=E2=80=AFAM wrote: > > From: Satha Rao > > When try to configure MTU for lower value causes run time failure > due to old bigger packets enqueued. To avoid error interrupts better > to flush the all SQs of this port before configuring new MTU. Added Fixes: 8589ec212e80 ("net/cnxk: support MTU set") Cc: stable@dpdk.org Applied to dpdk-next-net-mrvl/for-next-net. Thanks > > Signed-off-by: Satha Rao > --- > drivers/net/cnxk/cnxk_ethdev.h | 1 + > drivers/net/cnxk/cnxk_ethdev_ops.c | 47 ++++++++++++++++++++++++++++++++= ++++++ > 2 files changed, 48 insertions(+) > > diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethde= v.h > index e280d6c..45460ae 100644 > --- a/drivers/net/cnxk/cnxk_ethdev.h > +++ b/drivers/net/cnxk/cnxk_ethdev.h > @@ -446,6 +446,7 @@ int cnxk_nix_probe(struct rte_pci_driver *pci_drv, > struct rte_pci_device *pci_dev); > int cnxk_nix_remove(struct rte_pci_device *pci_dev); > int cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu); > +int cnxk_nix_sq_flush(struct rte_eth_dev *eth_dev); > int cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev, > struct rte_ether_addr *mc_addr_set, > uint32_t nb_mc_addr); > diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_e= thdev_ops.c > index bce6d59..da5ee19 100644 > --- a/drivers/net/cnxk/cnxk_ethdev_ops.c > +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c > @@ -496,6 +496,44 @@ > } > > int > +cnxk_nix_sq_flush(struct rte_eth_dev *eth_dev) > +{ > + struct cnxk_eth_dev *dev =3D cnxk_eth_pmd_priv(eth_dev); > + struct rte_eth_dev_data *data =3D eth_dev->data; > + int i, rc =3D 0; > + > + /* Flush all tx queues */ > + for (i =3D 0; i < eth_dev->data->nb_tx_queues; i++) { > + struct roc_nix_sq *sq =3D &dev->sqs[i]; > + > + if (eth_dev->data->tx_queues[i] =3D=3D NULL) > + continue; > + > + rc =3D roc_nix_tm_sq_aura_fc(sq, false); > + if (rc) { > + plt_err("Failed to disable sqb aura fc, rc=3D%d",= rc); > + goto exit; > + } > + > + /* Wait for sq entries to be flushed */ > + rc =3D roc_nix_tm_sq_flush_spin(sq); > + if (rc) { > + plt_err("Failed to drain sq, rc=3D%d\n", rc); > + goto exit; > + } > + if (data->tx_queue_state[i] =3D=3D RTE_ETH_QUEUE_STATE_ST= ARTED) { > + rc =3D roc_nix_tm_sq_aura_fc(sq, true); > + if (rc) { > + plt_err("Failed to enable sq aura fc, txq= =3D%u, rc=3D%d", i, rc); > + goto exit; > + } > + } > + } > +exit: > + return rc; > +} > + > +int > cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) > { > uint32_t old_frame_size, frame_size =3D mtu + CNXK_NIX_L2_OVERHEA= D; > @@ -538,6 +576,15 @@ > goto exit; > } > > + /* if new MTU was smaller than old one, then flush all SQs before= MTU change */ > + if (old_frame_size > frame_size) { > + if (data->dev_started) { > + plt_err("Reducing MTU is not supported when devic= e started"); > + goto exit; > + } > + cnxk_nix_sq_flush(eth_dev); > + } > + > frame_size -=3D RTE_ETHER_CRC_LEN; > > /* Update mtu on Tx */ > -- > 1.8.3.1 >