From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8E191A04F3; Fri, 20 Dec 2019 04:38:35 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B17A21BDFD; Fri, 20 Dec 2019 04:38:34 +0100 (CET) Received: from mail-io1-f66.google.com (mail-io1-f66.google.com [209.85.166.66]) by dpdk.org (Postfix) with ESMTP id 643A31B3BB for ; Fri, 20 Dec 2019 04:38:33 +0100 (CET) Received: by mail-io1-f66.google.com with SMTP id b10so7995697iof.11 for ; Thu, 19 Dec 2019 19:38:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=So6SdQqFJf8vC7NNZSH0FYiXHjzwb1xyDzKLvHrZ9ZA=; b=ixF4TVLBC0UYs+ECI0cEky0yrM08G7mZLgREuWPYzuNzE41ZnmpP0lMC2uvael85pg 4YcS6yEDN4yppESprNJudLFhp+WD3+jJAG9Phzn8DtyOfgPHPj8g2dSbvgbcBQ/qdO1G UVo0hJouZYWOfQj3cvh926GE8WQF8hwg6vpyG+2RaUJxBXFL2c/uo4qlr5Jc1GJLaWQJ 4+z9JzHU9CHL0k92HUv3XeOPRVG6CgU6DFX4FvJB8apgPtOEMaVp7/iEAp+xwdawoNQe 3ssQUDDGCzOWL5Knms9QhzpWCAoQGh1MxYi/xEdSRy3TTNWIgAXOeAu/VVSJ+knZ25Ry +p/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=So6SdQqFJf8vC7NNZSH0FYiXHjzwb1xyDzKLvHrZ9ZA=; b=cNfO7cwdUnMoyWXbSESaL+B5dZ4g5g1ExvyIkXFd9DJuEVTxhEq4mkh7VN2HRoWbfZ Nmd/Rn9zgeZEkpZRJB23e5r8+oalsSOR6RJDpI3O3Wj9FSAEWED/U7Iedffw7T1nFvMP HgNmQBfHJmX2yqipmu605SWNWotr0hqejzrYgH+N2cIA6+tUtj3+Dl4LzoozePKSAMMJ I1kbasKiGYrZf+6nw3RJfbKdgUyQHzenGBDhXv9Fx6ijV00qIPqh+Y1U3/sjl85yrjO5 GoTWYjpM5t+AtRMmyI6VLDz7tw5zso/2GzWFw4YPpKQ44PHh8HTu2ntQRxDMC2EuTjVX fqIQ== X-Gm-Message-State: APjAAAVkKV2Nl9svucNSL7TYaz31ZTfsi+sJmm/nEjNv+Dr6aBn/jpET Fjm87fJkD9kBEjAWDjfXvHgMXDtm8kmsrB1ZWLc= X-Google-Smtp-Source: APXvYqwCxbeusLcCE5ENryoe3FAkTtiqPAcwqd+AFEkoENGedQW616Yvc5WZZ2nCorLUiO6Qzd+Io19PGN7z8YaRgyY= X-Received: by 2002:a5e:8b44:: with SMTP id z4mr8567049iom.271.1576813112518; Thu, 19 Dec 2019 19:38:32 -0800 (PST) MIME-Version: 1.0 References: <1571758074-16445-1-git-send-email-gavin.hu@arm.com> <1576811391-19131-1-git-send-email-gavin.hu@arm.com> <1576811391-19131-2-git-send-email-gavin.hu@arm.com> In-Reply-To: From: Jerin Jacob Date: Fri, 20 Dec 2019 09:08:16 +0530 Message-ID: To: Gavin Hu Cc: dpdk-dev , nd , David Marchand , Thomas Monjalon , rasland@mellanox.com, maxime.coquelin@redhat.com, tiwei.bie@intel.com, Hemant Agrawal , Jerin Jacob , Pavan Nikhilesh , Honnappa Nagarahalli , "Ruifeng Wang (Arm Technology China)" , Phil Yang , Joyce Kong , Steve Capper Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for aarch64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, Dec 20, 2019 at 9:03 AM Jerin Jacob wrote: > > On Fri, Dec 20, 2019 at 8:40 AM Gavin Hu wrote: > > > > Armv8's peripheral coherence order is a total order on all reads and writes > > to that peripheral.[1] > > > > The peripheral coherence order for a memory-mapped peripheral signifies the > > order in which accesses arrive at the endpoint. For a read or a write RW1 > > and a read or a write RW2 to the same peripheral, then RW1 will appear in > > the peripheral coherence order for the peripheral before RW2 if either of > > the following cases apply: > > 1. RW1 and RW2 are accesses using Non-cacheable or Device attributes and > > RW1 is Ordered-before RW2. > > 2. RW1 and RW2 are accesses using Device-nGnRE or Device-nGnRnE attributes > > and RW1 appears in program order before RW2. > > > This is true if RW1 and RW2 addresses are device memory. i.e the > registers in the PCI bar address. > If RW1 is DDR address which is been used by the controller(say NIC > ring descriptor) then there will be an issue. > For example Intel i40e driver, the admin queue update in Host DDR > memory and it updates the doorbell. > In such a case, this patch will create an issue. Correct? Have you > checked this patch with ARM64 + XL710 controllers? > > Some of the legacy code is missing such barriers, that's the reason > for adding rte_io_* barrier. More details: https://dev.dpdk.narkive.com/DpIRqDuy/dpdk-dev-patch-v2-i40e-fix-eth-i40e-dev-init-sequence-on-thunderx > > > > > On arm platforms, all the PCI resources are mapped to nGnRE device memory > > [2], the above case 2 holds true, that means the peripheral coherence order > > applies here and just a compiler barrier is sufficient for rte io barriers. > > > > [1] Section B2.3.4 of ARMARM, https://developer.arm.com/docs/ddi0487/lates > > t/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ > > tree/drivers/pci/pci-sysfs.c#n1204 > > > > Signed-off-by: Gavin Hu > > Reviewed-by: Steve Capper > > Reviewed-by: Phil Yang > > --- > > lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > index 859ae12..fd63956 100644 > > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > @@ -34,11 +34,11 @@ extern "C" { > > > > #define rte_smp_rmb() dmb(ishld) > > > > -#define rte_io_mb() rte_mb() > > +#define rte_io_mb() rte_compiler_barrier() > > > > -#define rte_io_wmb() rte_wmb() > > +#define rte_io_wmb() rte_compiler_barrier() > > > > -#define rte_io_rmb() rte_rmb() > > +#define rte_io_rmb() rte_compiler_barrier() > > > > #define rte_cio_wmb() dmb(oshst) > > > > -- > > 2.7.4 > >