From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DFF2BA0C45; Thu, 16 Sep 2021 16:38:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BF0E04069E; Thu, 16 Sep 2021 16:38:07 +0200 (CEST) Received: from mail-io1-f48.google.com (mail-io1-f48.google.com [209.85.166.48]) by mails.dpdk.org (Postfix) with ESMTP id 521B640151 for ; Thu, 16 Sep 2021 16:38:06 +0200 (CEST) Received: by mail-io1-f48.google.com with SMTP id a15so8160717iot.2 for ; Thu, 16 Sep 2021 07:38:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=13EiRKQaWr+Q0sBtuX7Z9rIEu5pMFeRuu7BG7zra/MM=; b=cqGQx5Oeq76Xz2Yp/pAxDGYNOcDMtIMV40XUuMmvP5cNWnlPWly/UQ9VV7fp/N/KBI 2Zqv/F3ZqU9sG3i/GC8AevRGstV/2koYJExiID2nraJ08mo+Se/k0KmeWbwaZXBFsxxl o54GYf5k/edurMSfdFWMXb086WsCRlF5oMmSTF3vr807K+8u8TffTTiHPzO+ohSsmTuo XZXn6eF9tCG5FDzUyKyyqzRX2q7fNPn6LB6Tov2fA7xePA8nunAheB9kiEIzCuG4xcWx 8j3W6uiWxjcR0vNeJhJvEREMnUXB+lrnkjClmu4cw0rCIMFCqQ/me+43+ZeNy7XWyVWg ETxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=13EiRKQaWr+Q0sBtuX7Z9rIEu5pMFeRuu7BG7zra/MM=; b=KKTjwGT9OQgbI1dFV9/Ftd2qMQq7ODXExABWkSbMm77RLvXu8si5WoMEgtb6qC4exl 9coA4C9wuZlAHP2paRQvB2f6fiVLHCZy/mleVSX2p7i5Cu+QbrFdwmHxUIjVOEkG2Sci i1GxBizuFgLWlQsMYTDJiUABjh25zy/vjiywHgcjzInKrEENFP/8B+ekeTM5MuWPlgZG 2eDWyfqx0mVBjhjzuIAvtQinWOGLctM1jPbgw4deYpSkc7c3+Tqvwg6SakjhOn3SIDk9 AgkTi5N8SOOiryJfcISfQyrPY8XLuKDw4QY1Oa1wgpcunxQbZtBakFUpeD1EF+Q+N1X1 tC3g== X-Gm-Message-State: AOAM530WDQ+BSobTplgV6X2lWdZQJCEeulVJigJ5D03+QQ0VIs/F7Lgh J1DobqlG5bHtT6u6Vh4hATFaYZjuwibvhp1GJP+Jv+k0fEc= X-Google-Smtp-Source: ABdhPJxjO7WDmm87AScCO95Xr+MKXfew/aWuAK7ODJXS8ib3ONISgfq4a0iFMsPLgkvYUJ3oZmf0OpoVL7TIywFXI1c= X-Received: by 2002:a05:6638:35ac:: with SMTP id v44mr4623531jal.48.1631803085646; Thu, 16 Sep 2021 07:38:05 -0700 (PDT) MIME-Version: 1.0 References: <20210830140819.2610366-1-asekhar@marvell.com> <20210830162903.2736191-1-asekhar@marvell.com> In-Reply-To: <20210830162903.2736191-1-asekhar@marvell.com> From: Jerin Jacob Date: Thu, 16 Sep 2021 20:07:39 +0530 Message-ID: To: Ashwin Sekhar T K Cc: dpdk-dev , Jerin Jacob , Sunil Kumar Kori , Satha Koteswara Rao Kottidi , Pavan Nikhilesh , Kiran Kumar K , Satheesh Paul , Nithin Dabilpuram , Akhil Goyal Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH 1/2] common/cnxk: update roc models X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Mon, Aug 30, 2021 at 10:00 PM Ashwin Sekhar T K wrote: > > Update roc models. Please update git comment for more details on what is updated. > > Signed-off-by: Ashwin Sekhar T K > --- > drivers/common/cnxk/roc_model.c | 51 +++++++++++++++---------------- > drivers/common/cnxk/roc_model.h | 53 +++++++++++++++++++++++++-------- > 2 files changed, 67 insertions(+), 37 deletions(-) > > diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c > index bc255b53cc..e5aeabe2e2 100644 > --- a/drivers/common/cnxk/roc_model.c > +++ b/drivers/common/cnxk/roc_model.c > @@ -13,14 +13,14 @@ struct roc_model *roc_model; > > #define SOC_PART_CN10K 0xD49 > > -#define PART_106XX 0xB9 > -#define PART_105XX 0xBA > -#define PART_105XXN 0xBC > -#define PART_98XX 0xB1 > -#define PART_96XX 0xB2 > -#define PART_95XX 0xB3 > -#define PART_95XXN 0xB4 > -#define PART_95XXMM 0xB5 > +#define PART_106xx 0xB9 > +#define PART_105xx 0xBA > +#define PART_105xxN 0xBC > +#define PART_98xx 0xB1 > +#define PART_96xx 0xB2 > +#define PART_95xx 0xB3 > +#define PART_95xxN 0xB4 > +#define PART_95xxMM 0xB5 > #define PART_95O 0xB6 > > #define MODEL_IMPL_BITS 8 > @@ -44,20 +44,21 @@ static const struct model_db { > uint64_t flag; > char name[ROC_MODEL_STR_LEN_MAX]; > } model_db[] = { > - {VENDOR_ARM, PART_106XX, 0, 0, ROC_MODEL_CN106XX, "cn10ka"}, > - {VENDOR_ARM, PART_105XX, 0, 0, ROC_MODEL_CNF105XX, "cnf10ka"}, > - {VENDOR_ARM, PART_105XXN, 0, 0, ROC_MODEL_CNF105XXN, "cnf10kb"}, > - {VENDOR_CAVIUM, PART_98XX, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"}, > - {VENDOR_CAVIUM, PART_96XX, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"}, > - {VENDOR_CAVIUM, PART_96XX, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"}, > - {VENDOR_CAVIUM, PART_96XX, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"}, > - {VENDOR_CAVIUM, PART_95XX, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"}, > - {VENDOR_CAVIUM, PART_95XX, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"}, > - {VENDOR_CAVIUM, PART_95XXN, 0, 0, ROC_MODEL_CNF95XXN_A0, "cnf95xxn_a0"}, > - {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95XXO_A0, "cnf95O_a0"}, > - {VENDOR_CAVIUM, PART_95XXMM, 0, 0, ROC_MODEL_CNF95XXMM_A0, > - "cnf95xxmm_a0"} > -}; > + {VENDOR_ARM, PART_106xx, 0, 0, ROC_MODEL_CN106xx_A0, "cn10ka_a0"}, > + {VENDOR_ARM, PART_105xx, 0, 0, ROC_MODEL_CNF105xx_A0, "cnf10ka_a0"}, > + {VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"}, > + {VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"}, > + {VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"}, > + {VENDOR_CAVIUM, PART_96xx, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"}, > + {VENDOR_CAVIUM, PART_96xx, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"}, > + {VENDOR_CAVIUM, PART_96xx, 2, 1, ROC_MODEL_CN96xx_C0, "cn96xx_c1"}, > + {VENDOR_CAVIUM, PART_95xx, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"}, > + {VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"}, > + {VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"}, > + {VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"}, > + {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"}, > + {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0, > + "cnf95xxmm_a0"}}; > > static uint32_t > cn10k_part_get(void) > @@ -85,11 +86,11 @@ cn10k_part_get(void) > } > ptr++; > if (strcmp("cn10ka", ptr) == 0) { > - soc = PART_106XX; > + soc = PART_106xx; > } else if (strcmp("cnf10ka", ptr) == 0) { > - soc = PART_105XX; > + soc = PART_105xx; > } else if (strcmp("cnf10kb", ptr) == 0) { > - soc = PART_105XXN; > + soc = PART_105xxN; > } else { > plt_err("Unidentified 'CPU compatible': <%s>", ptr); > goto fclose; > diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h > index c1d11b77c6..a54f435b46 100644 > --- a/drivers/common/cnxk/roc_model.h > +++ b/drivers/common/cnxk/roc_model.h > @@ -15,13 +15,14 @@ struct roc_model { > #define ROC_MODEL_CN96xx_C0 BIT_ULL(2) > #define ROC_MODEL_CNF95xx_A0 BIT_ULL(4) > #define ROC_MODEL_CNF95xx_B0 BIT_ULL(6) > -#define ROC_MODEL_CNF95XXMM_A0 BIT_ULL(8) > -#define ROC_MODEL_CNF95XXN_A0 BIT_ULL(12) > -#define ROC_MODEL_CNF95XXO_A0 BIT_ULL(13) > +#define ROC_MODEL_CNF95xxMM_A0 BIT_ULL(8) > +#define ROC_MODEL_CNF95xxN_A0 BIT_ULL(12) > +#define ROC_MODEL_CNF95xxO_A0 BIT_ULL(13) > +#define ROC_MODEL_CNF95xxN_A1 BIT_ULL(14) > #define ROC_MODEL_CN98xx_A0 BIT_ULL(16) > -#define ROC_MODEL_CN106XX BIT_ULL(20) > -#define ROC_MODEL_CNF105XX BIT_ULL(21) > -#define ROC_MODEL_CNF105XXN BIT_ULL(22) > +#define ROC_MODEL_CN106xx_A0 BIT_ULL(20) > +#define ROC_MODEL_CNF105xx_A0 BIT_ULL(21) > +#define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22) > > uint64_t flag; > #define ROC_MODEL_STR_LEN_MAX 128 > @@ -31,11 +32,15 @@ struct roc_model { > #define ROC_MODEL_CN96xx_Ax (ROC_MODEL_CN96xx_A0 | ROC_MODEL_CN96xx_B0) > #define ROC_MODEL_CN9K \ > (ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \ > - ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95XXMM_A0 | \ > - ROC_MODEL_CNF95XXO_A0 | ROC_MODEL_CNF95XXN_A0 | ROC_MODEL_CN98xx_A0) > + ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 | \ > + ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \ > + ROC_MODEL_CNF95xxN_A1) > > +#define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0) > +#define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0) > +#define ROC_MODEL_CNF105xxN (ROC_MODEL_CNF105xxN_A0) > #define ROC_MODEL_CN10K \ > - (ROC_MODEL_CN106XX | ROC_MODEL_CNF105XX | ROC_MODEL_CNF105XXN) > + (ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN) > > /* Runtime variants */ > static inline uint64_t > @@ -105,6 +110,12 @@ roc_model_is_cn96_ax(void) > return (roc_model->flag & ROC_MODEL_CN96xx_Ax); > } > > +static inline uint64_t > +roc_model_is_cn96_cx(void) > +{ > + return (roc_model->flag & ROC_MODEL_CN96xx_C0); > +} > + > static inline uint64_t > roc_model_is_cn95_a0(void) > { > @@ -114,19 +125,37 @@ roc_model_is_cn95_a0(void) > static inline uint64_t > roc_model_is_cn10ka(void) > { > - return roc_model->flag & ROC_MODEL_CN106XX; > + return roc_model->flag & ROC_MODEL_CN106xx; > } > > static inline uint64_t > roc_model_is_cnf10ka(void) > { > - return roc_model->flag & ROC_MODEL_CNF105XX; > + return roc_model->flag & ROC_MODEL_CNF105xx; > } > > static inline uint64_t > roc_model_is_cnf10kb(void) > { > - return roc_model->flag & ROC_MODEL_CNF105XXN; > + return roc_model->flag & ROC_MODEL_CNF105xxN; > +} > + > +static inline uint64_t > +roc_model_is_cn10ka_a0(void) > +{ > + return roc_model->flag & ROC_MODEL_CN106xx_A0; > +} > + > +static inline uint64_t > +roc_model_is_cnf10ka_a0(void) > +{ > + return roc_model->flag & ROC_MODEL_CNF105xx_A0; > +} > + > +static inline uint64_t > +roc_model_is_cnf10kb_a0(void) > +{ > + return roc_model->flag & ROC_MODEL_CNF105xxN_A0; > } > > int roc_model_init(struct roc_model *model); > -- > 2.32.0 >