From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0BF7CA04AF; Mon, 4 May 2020 10:52:27 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 71A001D37E; Mon, 4 May 2020 10:52:26 +0200 (CEST) Received: from mail-il1-f194.google.com (mail-il1-f194.google.com [209.85.166.194]) by dpdk.org (Postfix) with ESMTP id A5E1B1D148 for ; Mon, 4 May 2020 10:52:25 +0200 (CEST) Received: by mail-il1-f194.google.com with SMTP id r2so10514650ilo.6 for ; Mon, 04 May 2020 01:52:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=e5yHA2EcX776x0whAq8/kgTIle3fssSgos1P/ZA4Eks=; b=EnYpMuOkP1JMqT8Ey/NIC0FkVA4iqUd24wHp3I1BIBCnI9UZYA/Pei8yg6ehjedqN2 zoPW8gMT3TuBSk7d9ZwtgcQyVh5LhzUWSTSOP0Ag3MYV+TTld0ZOY5Lq4WPhQJF3FhG3 aEXKHqEsCeNKQ0xOrbjXOl/H4JpL0MVN7c0pgVy+GAc8mrh0h0YQ4cX+uG53DXpwn6b/ 5YK/2z6UCeDQiBVNDk82u/GbrSOVwujcvBveVhrqPHpSdip2FDZ87r5q89376heeokJt UcWCyeJxRwrefUBYdPwLJ9Rxt4hj6Jm+FBqKGaQUaK46Cj1rUxc2dp/Ot+ll11nyxeMn tTgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=e5yHA2EcX776x0whAq8/kgTIle3fssSgos1P/ZA4Eks=; b=oUrQmdiNDmvgfkYjLU/Ncu8rkpGxHV5scOVrQ9M8aoklO0tXh+SFDRQgWfRtWnTFw1 OFV0TiYKNJY5ujhudeYmaAjdKgGQ+B2mC8Z8agKf3aD+GRQ84OvudCx4uKOpHt8fkm0N oWxnkj1mOtwYacFjzqexem3idrHyn9haFANNPKTeLAH/GHAzUZFWoW5UiF6bsKwaWmGv 9WKSOwuhLETbygjulvtnkFnL8TlRW3pbmexf1MR91ld3xZiAaaD2WjEKjWuwAasrWlNo zxcwBkhXDfoe7qEZfF6zE63wKMOP26ZsoqNTDvWMgQ1E1QQ1SRtzKRG4eyQ4HVUVHw1h /KzA== X-Gm-Message-State: AGi0PuanOP1Xgc5gN5h3SlHyNN4ZcAjLKbMuALeo6zmASt0lG1wjemat aSkiTDdVuTTakyQgXw6A5YN+rf4bAaWxsgFdsviVcUaD X-Google-Smtp-Source: APiQypJk8dBWxRjpRzzG03tfkm11w7kIPspywAeJiyrepKFya6J5SxR9Qm/S0ouE+1ksGL8bEWtF5bizPYss1IxE834= X-Received: by 2002:a92:8b45:: with SMTP id i66mr15105191ild.162.1588582344841; Mon, 04 May 2020 01:52:24 -0700 (PDT) MIME-Version: 1.0 References: <20200417064113.7459-1-nithind1988@gmail.com> <20200501142417.28243-1-nithind1988@gmail.com> In-Reply-To: <20200501142417.28243-1-nithind1988@gmail.com> From: Jerin Jacob Date: Mon, 4 May 2020 14:22:08 +0530 Message-ID: To: Nithin Dabilpuram Cc: Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K , dpdk-dev , Krzysztof Kanas Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v2] net/octeontx2: update red algo for shaper dynamic update X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, May 1, 2020 at 7:54 PM Nithin Dabilpuram wrote: > > From: Nithin Dabilpuram > > Due to an errata red algo needs to be set to discard instead of stall > for 96XX C0 silicon for two rate shaping. This workaround is being > already handled for newly created hierarchy but not for dynamic > shaper update cases. This patch hence applies the workaround > even when for shaper dynamic update. > > Signed-off-by: Nithin Dabilpuram > --- > v2: > - Rebased patch to fix dependency issue Applied to dpdk-next-net-mrvl/master. Thanks > > drivers/net/octeontx2/otx2_tm.c | 39 +++++++++++++++++++++++++++------------ > drivers/net/octeontx2/otx2_tm.h | 1 + > 2 files changed, 28 insertions(+), 12 deletions(-) > > diff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c > index f94618d..b57e10f 100644 > --- a/drivers/net/octeontx2/otx2_tm.c > +++ b/drivers/net/octeontx2/otx2_tm.c > @@ -237,6 +237,30 @@ shaper_config_to_nix(struct otx2_nix_tm_shaper_profile *profile, > &pir->burst_mantissa); > } > > +static void > +shaper_default_red_algo(struct otx2_eth_dev *dev, > + struct otx2_nix_tm_node *tm_node, > + struct otx2_nix_tm_shaper_profile *profile) > +{ > + struct shaper_params cir, pir; > + > + /* C0 doesn't support STALL when both PIR & CIR are enabled */ > + if (profile && otx2_dev_is_96xx_Cx(dev)) { > + memset(&cir, 0, sizeof(cir)); > + memset(&pir, 0, sizeof(pir)); > + shaper_config_to_nix(profile, &cir, &pir); > + > + if (pir.rate && cir.rate) { > + tm_node->red_algo = NIX_REDALG_DISCARD; > + tm_node->flags |= NIX_TM_NODE_RED_DISCARD; > + return; > + } > + } > + > + tm_node->red_algo = NIX_REDALG_STD; > + tm_node->flags &= ~NIX_TM_NODE_RED_DISCARD; > +} > + > static int > populate_tm_tl1_default(struct otx2_eth_dev *dev, uint32_t schq) > { > @@ -744,7 +768,6 @@ nix_tm_node_add_to_list(struct otx2_eth_dev *dev, uint32_t node_id, > { > struct otx2_nix_tm_shaper_profile *profile; > struct otx2_nix_tm_node *tm_node, *parent_node; > - struct shaper_params cir, pir; > uint32_t profile_id; > > profile_id = params->shaper_profile_id; > @@ -778,19 +801,9 @@ nix_tm_node_add_to_list(struct otx2_eth_dev *dev, uint32_t node_id, > if (profile) > profile->reference_count++; > > - memset(&cir, 0, sizeof(cir)); > - memset(&pir, 0, sizeof(pir)); > - shaper_config_to_nix(profile, &cir, &pir); > - > tm_node->parent = parent_node; > tm_node->parent_hw_id = UINT32_MAX; > - /* C0 doesn't support STALL when both PIR & CIR are enabled */ > - if (lvl < OTX2_TM_LVL_QUEUE && > - otx2_dev_is_96xx_Cx(dev) && > - pir.rate && cir.rate) > - tm_node->red_algo = NIX_REDALG_DISCARD; > - else > - tm_node->red_algo = NIX_REDALG_STD; > + shaper_default_red_algo(dev, tm_node, profile); > > TAILQ_INSERT_TAIL(&dev->node_list, tm_node, node); > > @@ -2500,6 +2513,8 @@ otx2_nix_tm_node_shaper_update(struct rte_eth_dev *eth_dev, > if (rc) > return rc; > > + shaper_default_red_algo(dev, tm_node, profile); > + > /* Update the PIR/CIR and clear SW XOFF */ > req = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox); > req->lvl = tm_node->hw_lvl; > diff --git a/drivers/net/octeontx2/otx2_tm.h b/drivers/net/octeontx2/otx2_tm.h > index 9675182..4a80c23 100644 > --- a/drivers/net/octeontx2/otx2_tm.h > +++ b/drivers/net/octeontx2/otx2_tm.h > @@ -46,6 +46,7 @@ struct otx2_nix_tm_node { > #define NIX_TM_NODE_HWRES BIT_ULL(0) > #define NIX_TM_NODE_ENABLED BIT_ULL(1) > #define NIX_TM_NODE_USER BIT_ULL(2) > +#define NIX_TM_NODE_RED_DISCARD BIT_ULL(3) > /* Shaper algorithm for RED state @NIX_REDALG_E */ > uint32_t red_algo:2; > > -- > 2.8.4 >