From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 42F7B42BD1; Mon, 29 May 2023 11:14:56 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B7F98410DD; Mon, 29 May 2023 11:14:55 +0200 (CEST) Received: from mail-vs1-f52.google.com (mail-vs1-f52.google.com [209.85.217.52]) by mails.dpdk.org (Postfix) with ESMTP id 9AE66410D7 for ; Mon, 29 May 2023 11:14:54 +0200 (CEST) Received: by mail-vs1-f52.google.com with SMTP id ada2fe7eead31-438f80597d8so953627137.0 for ; Mon, 29 May 2023 02:14:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1685351694; x=1687943694; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=z4DLBqbn4sf4MemBL1kmOsqYUM1Sj+50JeWNY96Zv3k=; b=VYu00Xj1lqRMIts8S4GS3jKnp3d7oOsKNPYAs7j6MA9zFHZIbzYm9qSzkFlYuJn3pB i3LXUpn/5cdEo156BqCzVipqhF1dQjxZDuxWT3BQU4OecK4+Jbcbl+uooQxU9GbzDwG1 i22PwpIU8zXDm2ORlUd6Vyf62TLbONVE2cLMxjplOYtJfPD6bdboKkZOnwA4u7RCgX7p LCkyfJkYwSWA6lPVJAQdoClFi02im0Ht4mGSkSxMYLvvs2JVnL4UtFcas+/rUjNa6XQT 0rCoApfJ2fEeqLn3ik3DY27NteB9vzPJLBmizznk2rA3RsGcTGHIs0+nyJJGBOCYs5J3 3uzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685351694; x=1687943694; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z4DLBqbn4sf4MemBL1kmOsqYUM1Sj+50JeWNY96Zv3k=; b=HxAJKw3gEFAMb/S15C1aL0fYHH/9wYCAGTLHzpQSSgSd04N+sBHBZgQiIC4SgNj231 l8bFas0rMuxjiNEkSsDH80SUkpfXZuE3YK5XNF/Pe2959Vt+RqeVz2/W9M5NyEWLNyqH q6IOPlrDZjyz2rG7GO1Cw/ZgPi5tu7COVvMGghHln7/tCKZLuwV+CMCl94SIMuaf6xi6 A2mdels2TRt1Y1wuRWOr1Tlkq5URw7EmS71RrZHf+92s754g1wSZ3IiSRhrWZfcIxybm XB/fPqGjSCYmrs6v2wM+c4hfs7GP0pt0pxm+iNwMdHb6qCRDbx6EOMFP/NAP3OpVdvOV fTEg== X-Gm-Message-State: AC+VfDzX5QEoFDizLzQGFFtGFLZ8MvQ3ClDfBVbW1Ow/2c4ZEX7zzLbf guziaEgy2Iu18LEBYv0+BJFoUDoG1dHdRVrXWc4sH+g+Xvs= X-Google-Smtp-Source: ACHHUZ4wNE26tAUTRy9Rp4BxACVrqi5ply4vuqrzZWqz8tjaAIvcWl77DOHdubU9qn05bNPEol2T6+7Ig4hsZ9dXSk8= X-Received: by 2002:a67:ff8a:0:b0:439:35d4:1aa1 with SMTP id v10-20020a67ff8a000000b0043935d41aa1mr3061113vsq.30.1685351693829; Mon, 29 May 2023 02:14:53 -0700 (PDT) MIME-Version: 1.0 References: <20230526134507.885354-1-asekhar@marvell.com> In-Reply-To: <20230526134507.885354-1-asekhar@marvell.com> From: Jerin Jacob Date: Mon, 29 May 2023 14:44:27 +0530 Message-ID: Subject: Re: [PATCH 1/2] mempool/cnxk: avoid indefinite wait To: Ashwin Sekhar T K Cc: dev@dpdk.org, Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Pavan Nikhilesh , jerinj@marvell.com, psatheesh@marvell.com, anoobj@marvell.com, gakhil@marvell.com, hkalra@marvell.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Fri, May 26, 2023 at 7:15=E2=80=AFPM Ashwin Sekhar T K wrote: > > Avoid waiting indefinitely when counting batch alloc > pointers by adding a wait timeout. Please add Fixes: and change the subject starts with "fix ..." > > Signed-off-by: Ashwin Sekhar T K > --- > drivers/common/cnxk/roc_npa.h | 15 +++++++++------ > drivers/mempool/cnxk/cn10k_mempool_ops.c | 3 ++- > 2 files changed, 11 insertions(+), 7 deletions(-) > > diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.= h > index 21608a40d9..d3caa71586 100644 > --- a/drivers/common/cnxk/roc_npa.h > +++ b/drivers/common/cnxk/roc_npa.h > @@ -241,19 +241,23 @@ roc_npa_aura_batch_alloc_issue(uint64_t aura_handle= , uint64_t *buf, > } > > static inline void > -roc_npa_batch_alloc_wait(uint64_t *cache_line) > +roc_npa_batch_alloc_wait(uint64_t *cache_line, unsigned int wait_us) > { > + const uint64_t ticks =3D (uint64_t)wait_us * plt_tsc_hz() / (uint= 64_t)1E6; > + const uint64_t start =3D plt_tsc_cycles(); > + > /* Batch alloc status code is updated in bits [5:6] of the first = word > * of the 128 byte cache line. > */ > while (((__atomic_load_n(cache_line, __ATOMIC_RELAXED) >> 5) & 0x= 3) =3D=3D > ALLOC_CCODE_INVAL) > - ; > + if (wait_us && (plt_tsc_cycles() - start) >=3D ticks) > + break; > } > > static inline unsigned int > roc_npa_aura_batch_alloc_count(uint64_t *aligned_buf, unsigned int num, > - unsigned int do_wait) > + unsigned int wait_us) > { > unsigned int count, i; > > @@ -267,8 +271,7 @@ roc_npa_aura_batch_alloc_count(uint64_t *aligned_buf,= unsigned int num, > > status =3D (struct npa_batch_alloc_status_s *)&aligned_bu= f[i]; > > - if (do_wait) > - roc_npa_batch_alloc_wait(&aligned_buf[i]); > + roc_npa_batch_alloc_wait(&aligned_buf[i], wait_us); > > count +=3D status->count; > } > @@ -293,7 +296,7 @@ roc_npa_aura_batch_alloc_extract(uint64_t *buf, uint6= 4_t *aligned_buf, > > status =3D (struct npa_batch_alloc_status_s *)&aligned_bu= f[i]; > > - roc_npa_batch_alloc_wait(&aligned_buf[i]); > + roc_npa_batch_alloc_wait(&aligned_buf[i], 0); > > line_count =3D status->count; > > diff --git a/drivers/mempool/cnxk/cn10k_mempool_ops.c b/drivers/mempool/c= nxk/cn10k_mempool_ops.c > index ba826f0f01..ff0015d8de 100644 > --- a/drivers/mempool/cnxk/cn10k_mempool_ops.c > +++ b/drivers/mempool/cnxk/cn10k_mempool_ops.c > @@ -9,6 +9,7 @@ > > #define BATCH_ALLOC_SZ ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS > #define BATCH_OP_DATA_TABLE_MZ_NAME "batch_op_data_table_mz" > +#define BATCH_ALLOC_WAIT_US 5 > > enum batch_op_status { > BATCH_ALLOC_OP_NOT_ISSUED =3D 0, > @@ -178,7 +179,7 @@ cn10k_mempool_get_count(const struct rte_mempool *mp) > > if (mem->status =3D=3D BATCH_ALLOC_OP_ISSUED) > count +=3D roc_npa_aura_batch_alloc_count( > - mem->objs, BATCH_ALLOC_SZ, 1); > + mem->objs, BATCH_ALLOC_SZ, BATCH_ALLOC_WA= IT_US); > > if (mem->status =3D=3D BATCH_ALLOC_OP_DONE) > count +=3D mem->sz; > -- > 2.25.1 >