From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ot0-f193.google.com (mail-ot0-f193.google.com [74.125.82.193]) by dpdk.org (Postfix) with ESMTP id A89D716E for ; Sun, 14 Jan 2018 07:51:28 +0100 (CET) Received: by mail-ot0-f193.google.com with SMTP id s3so8292165otc.9 for ; Sat, 13 Jan 2018 22:51:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=/SVueZQUOYZ4zSlmlUzhLwLnlG6uwntFE87in72gLX4=; b=HWaXLcrFt8wjy0y30PBrlbEhp4Av/ID1eff80gNeuVk8WydBD7Qto0kRZMTZCgqReF vl8oKteLgn36ewblDYIpg7ZmD2B30oXzis7NRZIVKXJELoOb4ESl+c1Kige6phHgnIaY LKc9hOvMIJTnm1eb3tIwaYWe91d4aLHhR4qZtx8VRy+hiSKY4PhpxGrLvqJYqRVXmOYj +eusxEvppr7u3M+f33G5IBYsigDajg2RxlmOy8JlJgj02Zd5IJIdAgJxS4vVVr0zWZ1x 9irWAhOlTXdqDcwuejCiWOEtSVyFL4mTRSo5c/b4P0/LdMkcj+9/mNqWFe3s76O0WgLC Q9YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=/SVueZQUOYZ4zSlmlUzhLwLnlG6uwntFE87in72gLX4=; b=c3hoxP7H3gHL8na4SOxYaPe2XQ/CAq/OTTGFXqjWKI2cURiOdR7XTrXLasTJR94A5Y byfbsnvMlbFQjxi1opwwCwmO95onY7j49t1jZDOZZlpxVTnf4PTvGcyDZ7w6QU6f9Ggy 11IOkivsFfi4lkls7QX2GrFlOCZmJJs12m3DCamZBbz4+RlyQnxNvz5y2ZvKKCfY4jV6 Ue4+MBTbwBd8j5RAF9O6/Mv8u/lXsZ1iQWKFD35uKg4YBxzUCyF7QhT9kGOhiGzlwJKF ZpVKH6tabbRGv4pLqMcWq8iYMsvjKEA68LieK+lBT5FtdHz05yNv/zaHqG5fpIms10ot FFIg== X-Gm-Message-State: AKwxyteStgysmOMX+v4eIxqr0eGTjkhWbxKdXe67IgFaX6o6F8vmpl/d sNUBiYDJukOB3EizHoSDYAnwlBEbY3ydQ8r1VvUZUvGj X-Google-Smtp-Source: ACJfBoviiGu6nTUEmk+0knUUH52DixhiZWZpejwfCu+EdY1K/JtELYOKFOa+3WlJYJziPHK3y6uKRkbHk/QV0jHQAp8= X-Received: by 10.157.54.100 with SMTP id w91mr3932237otb.136.1515912687989; Sat, 13 Jan 2018 22:51:27 -0800 (PST) MIME-Version: 1.0 Received: by 10.74.151.65 with HTTP; Sat, 13 Jan 2018 22:51:27 -0800 (PST) In-Reply-To: <49759EB36A64CF4892C1AFEC9231E8D66CF21CE1@PGSMSX112.gar.corp.intel.com> References: <1515161439-4792-1-git-send-email-xiangxia.m.yue@gmail.com> <1515161439-4792-4-git-send-email-xiangxia.m.yue@gmail.com> <94479800C636CB44BD422CB454846E013208AC68@SHSMSX101.ccr.corp.intel.com> <49759EB36A64CF4892C1AFEC9231E8D66CF21CE1@PGSMSX112.gar.corp.intel.com> From: Tonghao Zhang Date: Sun, 14 Jan 2018 14:51:27 +0800 Message-ID: To: "Dai, Wei" Cc: "Xing, Beilei" , "dev@dpdk.org" Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH 4/5] net/ixgbevf: add check for rte_intr_enable. X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 14 Jan 2018 06:51:28 -0000 On Fri, Jan 12, 2018 at 8:10 PM, Dai, Wei wrote: > Hi, Tonghao > Thanks for your patch. > It looks that same change can be applied to ixgbe_dev_interrupt_action( ) > and ixgbe_dev_interrupt_delayed_handler( ). Yes, but the irq (e.g mailbox irq) is not same as rx interrupt handled frequently. and it will not affect the performance. > Anyway, you can test all these changes with example/l3fwd-power. > -Wei I tested them with example/l3fwd-power and our apps. It is ok. I will send v3 to you. > >> -----Original Message----- >> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Xing, Beilei >> Sent: Thursday, January 11, 2018 3:06 PM >> To: Tonghao Zhang ; dev@dpdk.org >> Subject: Re: [dpdk-dev] [PATCH 4/5] net/ixgbevf: add check for >> rte_intr_enable. >> >> >> >> > -----Original Message----- >> > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Tonghao Zhang >> > Sent: Friday, January 5, 2018 10:11 PM >> > To: dev@dpdk.org >> > Cc: Tonghao Zhang >> > Subject: [dpdk-dev] [PATCH 4/5] net/ixgbevf: add check for >> rte_intr_enable. >> >> The patch is not only for ixgbevf, but also for ixgbe, right? >> so how about changing the title with net/ixgbe started? >> >> > When we bind the ixgbevf to vfio and call the >> > rte_eth_dev_rx_intr_enable and rte_eth_dev_rx_intr_disable frequently, >> > the interrupt setting >> > (msi_set_mask_bit) will take more CPU as show below. rte_intr_enable >> > call the ioctl to map the fd to interrupts frequently. >> > >> > perf top: >> > 5.45% [kernel] [k] msi_set_mask_bit >> > >> > It is unnecessary to call the rte_intr_enable in >> > ixgbe_dev_rx_queue_intr_enable. because the fds has been mapped to >> > interrupt and not unmapped in ixgbe_dev_rx_queue_intr_disable. >> > >> > This patch add checks for using VFIO. With the patch, >> > msi_set_mask_bit is not listed in perl any more. Any suggestion will be >> welcome. >> > >> > Signed-off-by: Tonghao Zhang >> > --- >> > drivers/net/ixgbe/ixgbe_ethdev.c | 9 +++++++-- >> > 1 file changed, 7 insertions(+), 2 deletions(-) >> > >> > diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c >> > b/drivers/net/ixgbe/ixgbe_ethdev.c >> > index e929235..79e4097 100644 >> > --- a/drivers/net/ixgbe/ixgbe_ethdev.c >> > +++ b/drivers/net/ixgbe/ixgbe_ethdev.c >> > @@ -5610,7 +5610,9 @@ static void ixgbevf_set_vfta_all(struct >> > rte_eth_dev *dev, bool on) >> > RTE_SET_USED(queue_id); >> > IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); >> > >> > - rte_intr_enable(intr_handle); >> > + if (intr_handle->type == RTE_INTR_HANDLE_UIO || >> > + intr_handle->type == RTE_INTR_HANDLE_UIO_INTX) >> > + rte_intr_enable(intr_handle); >> >> For igb_uio, did you check if it's necessary to call rte_intr_enable every time? >> Since rte interrupt is not disabled during ixgbevf_dev_rx_queue_intr_disable. >> >> > >> > return 0; >> > } >> > @@ -5659,7 +5661,10 @@ static void ixgbevf_set_vfta_all(struct >> > rte_eth_dev *dev, bool on) >> > mask &= (1 << (queue_id - 32)); >> > IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); >> > } >> > - rte_intr_enable(intr_handle); >> > + >> > + if (intr_handle->type == RTE_INTR_HANDLE_UIO || >> > + intr_handle->type == RTE_INTR_HANDLE_UIO_INTX) >> > + rte_intr_enable(intr_handle); >> >> The same comment as above. >> >> > >> > return 0; >> > } >> > -- >> > 1.8.3.1 >