From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qe0-f50.google.com (mail-qe0-f50.google.com [209.85.128.50]) by dpdk.org (Postfix) with ESMTP id 72C91232 for ; Tue, 18 Jun 2013 03:28:08 +0200 (CEST) Received: by mail-qe0-f50.google.com with SMTP id f6so2118353qej.37 for ; Mon, 17 Jun 2013 18:28:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=sDKvkHPhMO7wY8UocQ4Wj9j5SMLrskALxgfCFypxug8=; b=YfpKEKv8CdKgDd4hD8vM/u1Wkp0dm+oqmX9+5f6UV3Mpexh87GaclJ+9tdbPWIqZPi cbAMjW91lu+3/1Vk9Z9slNcOwREed6DJgM5gEJ5hD/751pFut7KDT7ZqYW7yzEuNZ3OT TSnkrtZiS05tgERGEcJ4HoNPqmlQRdEm0x+8uJ1cK1U04PHdqj+VSjbHx8+Cw/OaFbjv Z/PEjCEEP+lsH+ObFZ1HZPtAQ4NWv4m9EB1j4Yjx2tMnjMKbTMJ6b9oJB1PEZtkNl9NQ ekJN1GvMOyix+RzC4HdwiZazJC5X/okXSczR2u0LOEkr4yDUuXKM6mamIVWxgzfDwJRl LoMw== MIME-Version: 1.0 X-Received: by 10.224.58.142 with SMTP id g14mr10642681qah.67.1371518899623; Mon, 17 Jun 2013 18:28:19 -0700 (PDT) Received: by 10.224.101.193 with HTTP; Mon, 17 Jun 2013 18:28:19 -0700 (PDT) In-Reply-To: <20130605143337.76af91ff@nehalam.linuxnetplumber.net> References: <20130530171234.301927271@vyatta.com> <20130530171627.005239011@vyatta.com> <51AF501B.5060306@6wind.com> <20130605084927.34f138c1@nehalam.linuxnetplumber.net> <51AF7DDB.1070005@6wind.com> <20130605143337.76af91ff@nehalam.linuxnetplumber.net> Date: Tue, 18 Jun 2013 06:58:19 +0530 Message-ID: From: somnath kotur To: Stephen Hemminger Content-Type: multipart/alternative; boundary=20cf3074b470d0ab9a04df63a0f6 Cc: dev@dpdk.org Subject: Re: [dpdk-dev] [PATCH 5/7] pci: support multiple PCI regions per device X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Jun 2013 01:28:08 -0000 --20cf3074b470d0ab9a04df63a0f6 Content-Type: text/plain; charset=ISO-8859-1 Hi Any idea on the ETA for this patch? I'm presuming it's all good to be pulled into the mainline otherwise? Thanks Som On Thu, Jun 6, 2013 at 3:03 AM, Stephen Hemminger < stephen@networkplumber.org> wrote: > On Wed, 05 Jun 2013 20:05:15 +0200 > Damien Millescamps wrote: > > > On 06/05/2013 05:49 PM, Stephen Hemminger wrote: > > > On Wed, 05 Jun 2013 16:50:03 +0200 > > > Damien Millescamps wrote: > > > > > >> Hi Stephen, > > >> > > >> Overall this patch is very nice. My only comment on this one is why do > > >> you limit the max number of memory resources to 5 ? > > >> The PCI configuration space permits to store up to 6 base addresses. > > >> > > >>> +#define PCI_MEM_RESOURCE 5 > > >> Please, can you add a log/comment with your patch, too ? > > >> > > >> > > >> Cheers, > > > Only because I was trying to save some space, and I didn't see any > hardware > > > with that many useful regions. Also the kernel UIO driver has some > control > > > over which regions get exposed. > > > > I agree that hardware generally don't use that much BAR for the PCIe. > > However, this is only a matter of 20 to 24 Bytes, so I don't see any > > reason not defining this macro as per the PCI standard value. > > > > Could you add a commit log and change that so it can be ack'd and pushed > > in the DPDK repository ? > > > > Thanks, > > Go ahead and change the 5 to a 7. > No point in another resend of whole pile. > --20cf3074b470d0ab9a04df63a0f6 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
Hi
=A0Any idea on the ETA for this patch? I'= m presuming it's all good to be pulled into the mainline otherwise?

Thanks
Som


On Thu, Jun 6, 2013 at 3:03 AM, Stephen = Hemminger <stephen@networkplumber.org> wrote:
On Wed, 05 Jun 2013 20:05:15 +0200
Damien Millescamps <damien.millescamps@6wind.com> wrote:

> On 06/05/2013 05:49 PM, Stephen Hemminger wrote:
> > On Wed, 05 Jun 2013 16:50:03 +0200
> > Damien Millescamps <damien.millescamps@6wind.com> wrote:
> >
> >> Hi Stephen,
> >>
> >> Overall this patch is very nice. My only comment on this one = is why do
> >> you limit the max number of memory resources to 5 ?
> >> The PCI configuration space permits to store up to 6 base add= resses.
> >>
> >>> +#define PCI_MEM_RESOURCE 5
> >> Please, can you add a log/comment with your patch, too ?
> >>
> >>
> >> Cheers,
> > Only because I was trying to save some space, and I didn't se= e any hardware
> > with that many useful regions. Also the kernel UIO driver has som= e control
> > over which regions get exposed.
>
> I agree that hardware generally don't use that much BAR for the PC= Ie.
> However, this is only a matter of 20 to 24 Bytes, so I don't see a= ny
> reason not defining this macro as per the PCI standard value.
>
> Could you add a commit log and change that so it can be ack'd and = pushed
> in the DPDK repository ?
>
> Thanks,

Go ahead and change the 5 to a 7.
No point in another resend of whole pile.

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