From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3C6D1A052A; Fri, 10 Jul 2020 14:44:19 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A43F51D6A4; Fri, 10 Jul 2020 14:44:18 +0200 (CEST) Received: from mail-ej1-f65.google.com (mail-ej1-f65.google.com [209.85.218.65]) by dpdk.org (Postfix) with ESMTP id 986271D67E for ; Fri, 10 Jul 2020 14:44:17 +0200 (CEST) Received: by mail-ej1-f65.google.com with SMTP id ga4so5864812ejb.11 for ; Fri, 10 Jul 2020 05:44:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iol.unh.edu; s=unh-iol; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=3SWvRfUZD6F0Ltj+GAJJMJvjtCLZp5h7bA4yInMH1Ls=; b=hJ1/aku1rTz7ag7GU92ZRcmdWkEcg0TIP5uVRjab9RBKsJRlPwxQYP234V1PNbK0zd /+mWZIJogLCGNsO05DzALV67J9lHYBkyPKGDCOZfjLfMicgzeBlTE6hEZkgHV6XsUfwR P9GD/QtmfIJKDT4sZ6xNkJxXFoUW5I5kQqxXw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=3SWvRfUZD6F0Ltj+GAJJMJvjtCLZp5h7bA4yInMH1Ls=; b=KI8XUEuPu1yXhqBFe5Yvgi9LOpDCu6mFfs7FhRCoXYxUXH37W/k9KFeRnat7+s9UTZ lEh7VvU9q6K8bFUeml00U9TM+SZUGeniLIdC1bBCjQ2IleQaYEGaXkXvVjQkzw3zkHJv rEk+g2frfSDSaQ3WsCgX3uYTPwbkTuotntCE1KlqqTNKv2hsZgNdAEdKG+sMHu1AwYiu cCYNWffnnow9/ZLqSZAVTlaGOYnEkurGihEzIQg/RIsEDtbee53qXzaompwOK84VC7iD ElefOOgvdVAYmrN3hyNPkdLbyPe78laxCmTA4xn3+dECLNjO19kJHB+tQpyjys4Q05Yk Sxgg== X-Gm-Message-State: AOAM531n7QvpBvevRc1Smo/UQX/BXPaNmwmybP+zncSgLXXTDJU7U56Q G3yAzzeUAYVaA8zZet1RxPoJnPCKt+kiG+CII48OTQ== X-Google-Smtp-Source: ABdhPJxmlZA6KXfIWiXFVs9wvnstFu3xTDZ8YSxfCaRPohkkTXD3cAbjoE3uEzj6lSq1WZ6sYSjt17FmhO6SxwB6pDM= X-Received: by 2002:a17:906:d784:: with SMTP id pj4mr59297319ejb.405.1594385057284; Fri, 10 Jul 2020 05:44:17 -0700 (PDT) MIME-Version: 1.0 References: <20200708092435.9776-1-alvinx.zhang@intel.com> <3033441.08XpM1RNeG@thomas> In-Reply-To: <3033441.08XpM1RNeG@thomas> From: Lincoln Lavoie Date: Fri, 10 Jul 2020 08:43:37 -0400 Message-ID: To: Thomas Monjalon Cc: "Zhang, AlvinX" , dev@dpdk.org, Beilei Xing , Jeff Guo , David Marchand , anatoly.burakov@intel.com, ci@dpdk.org, Ferruh Yigit , "Richardson, Bruce" , "Xu, Qian Q" , john.mcnamara@intel.com, talshn@mellanox.com, Raslan Darawsheh , asafp@mellanox.com Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-dev] [dpdk-ci] [PATCH] bus/pci: fix mmap PCI resource X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, Jul 10, 2020 at 6:08 AM Thomas Monjalon wrote: > 10/07/2020 11:54, David Marchand: > > On Wed, Jul 8, 2020 at 11:26 AM wrote: > > > From: Alvin Zhang > > > > > > When mapping a PCI BAR containing an MSI-X table, some devices do not > > > need to actually map this BAR or only need to map part of them, which > > > may cause the mapping to fail. Now some checks are added and a non-NULL > > > initial value is set to the variable to avoid this situation. > > Note: this regression would not have happened if we had some CI tests > for simple device probing. > Please let's invest more in CI. > > Are you referring to adding tests to specifically check these conditions, or would this have been caught just from the continued expansion of testing on real hardware / NICs, or both? It seems like the issue is caused by a combination of hardware behaviors and "broken code". My point is, without having some of those behaviors in the CI, we might still not have caught this issue, even with probing checks. Of course, more checks are always a good thing. > > > > Fixes: 2fd3567e5425 ("pci: use OS generic memory mapping functions") > > > Cc: talshn@mellanox.com > > No he was not Cc in the thread. Same for Anatoly. > Adding more people in Cc... > > > > Signed-off-by: Alvin Zhang > > > --- > > > --- a/drivers/bus/pci/linux/pci_vfio.c > > > +++ b/drivers/bus/pci/linux/pci_vfio.c > > > @@ -547,6 +547,14 @@ > > > bar_index, > > > memreg[0].offset, memreg[0].size, > > > memreg[1].offset, memreg[1].size); > > > + > > > + if (memreg[0].size == 0 && memreg[1].size == 0) { > > > + /* No need to map this BAR */ > > > + RTE_LOG(DEBUG, EAL, "Skipping BAR%d\n", > bar_index); > > > + bar->size = 0; > > > + bar->addr = 0; > > > + return 0; > > > + } > > > > We already have a check on bar size == 0. > > Why would we have this condition? > > Broken hw? > > > > > > > } else { > > > memreg[0].offset = bar->offset; > > > memreg[0].size = bar->size; > > > @@ -556,7 +564,9 @@ > > > bar_addr = mmap(bar->addr, bar->size, 0, MAP_PRIVATE | > > > MAP_ANONYMOUS | additional_flags, -1, 0); > > > if (bar_addr != MAP_FAILED) { > > > - void *map_addr = NULL; > > > + /* Set non NULL initial value for in case of no PCI > mapping */ > > > + void *map_addr = bar_addr; > > > + > > > > It took me some time to understand this code... > > Anyway, we have a regression in the librte_pci. > > This is where the fix should be. > > Yes, I am going to send a fix. > > > We can cleanup this code later. > > Yes please, this function isn't understandable and lack of comments. > Anatoly please? > > > -- *Lincoln Lavoie* Senior Engineer, Broadband Technologies 21 Madbury Rd., Ste. 100, Durham, NH 03824 lylavoie@iol.unh.edu https://www.iol.unh.edu +1-603-674-2755 (m)