From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw0-f180.google.com (mail-yw0-f180.google.com [209.85.161.180]) by dpdk.org (Postfix) with ESMTP id 375362952 for ; Fri, 12 May 2017 07:51:03 +0200 (CEST) Received: by mail-yw0-f180.google.com with SMTP id b68so6388601ywe.3 for ; Thu, 11 May 2017 22:51:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=kOT1pjSh1SafJpD4yLHJTfFHwOXQlE/rb8qPRzE1AEM=; b=HW202OTiBy1pc5/uGW2DR5VHeCr8f8a1ubCPQ4AMBH6i5XD42/qx43nQcKcb6WA1jZ 771MruvgZN4fDpyAsyvPrDPPiAffS4CtXWNwEgrSEpZ7COpSYerXjACWuywLIV666CXc ewGQCH6QjC8PrIMfemIFrVLQUGhoo8B9CBNpE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=kOT1pjSh1SafJpD4yLHJTfFHwOXQlE/rb8qPRzE1AEM=; b=i+p0zfP4bo8yqhLKkhuV7QM6AdTzsofo6ZdQEX5UYHWJu5CUPVYsC2gDC5LaaBZMqd xY0IDRvr9D9HbPo9w/XEO3Gk+iikXChbW06QssEBFWz/bmRLomYNRCn9G+qIN3K6xtD/ uFdBvDCtj3D4nylFpkAIJIN/bHDio51VjfFmLz4buQOKEuZmlQYnoKnKgSeyAWtMGa+z uSD//e+mDyUGWs6PQWp21TngzZ+fIIvIawKJat2kuVyrhPc9JSyfjA9BAQ7pLHzPDEe3 0Nm3CPE5xoljZUtwqFMdVjwsu6HxGQLRfylyjFjyx6a3Ds/MQdv1OnLR9iog+ZOWl41K z1Ww== X-Gm-Message-State: AODbwcCFj5p/2oI+OyeoLd0skEH9PRdi3tZqp+F6zp34suJfM0qFzpVq Qg+leoIHUB1ZhNB5sQlPe8ti77O/V3yv X-Received: by 10.129.78.73 with SMTP id c70mr1792541ywb.62.1494568262350; Thu, 11 May 2017 22:51:02 -0700 (PDT) MIME-Version: 1.0 Received: by 10.37.4.16 with HTTP; Thu, 11 May 2017 22:51:01 -0700 (PDT) In-Reply-To: <20170509095341.10734-3-ashwin.sekhar@caviumnetworks.com> References: <20170427140618.35897-1-ashwin.sekhar@caviumnetworks.com> <20170509095341.10734-1-ashwin.sekhar@caviumnetworks.com> <20170509095341.10734-3-ashwin.sekhar@caviumnetworks.com> From: Jianbo Liu Date: Fri, 12 May 2017 13:51:01 +0800 Message-ID: To: Ashwin Sekhar T K Cc: cristian.dumitrescu@intel.com, thomas@monjalon.net, jasvinder.singh@intel.com, Jan Viktorin , Jerin Jacob , dev@dpdk.org Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v4 3/4] net: add arm64 neon version of CRC compute APIs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 May 2017 05:51:03 -0000 On 9 May 2017 at 17:53, Ashwin Sekhar T K wrote: > Added CRC compute APIs for arm64 utilizing the pmull > capability > > Added new file net_crc_neon.h to hold the arm64 pmull > CRC implementation > > Verified the changes with crc_autotest unit test case > > Signed-off-by: Ashwin Sekhar T K > --- > v2: > * Fixed merge conflict in MAINTAINERS > > v3: > * Moved feature detection changes and GCC_VERSION definition > changes to separate commit > * Replaced usage of assert() with RTE_ASSERT() > * Made the comments in rte_vect.h more positive in sense > > v4: > * Rebased on top of latest commit > > MAINTAINERS | 1 + > lib/librte_eal/common/include/arch/arm/rte_vect.h | 28 ++ > lib/librte_net/net_crc_neon.h | 357 ++++++++++++++++++++++ > lib/librte_net/rte_net_crc.c | 34 ++- > lib/librte_net/rte_net_crc.h | 2 + > 5 files changed, 416 insertions(+), 6 deletions(-) > create mode 100644 lib/librte_net/net_crc_neon.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index b6495d2..66d64c2 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -147,6 +147,7 @@ F: lib/librte_eal/common/include/arch/arm/*_64.h > F: lib/librte_acl/acl_run_neon.* > F: lib/librte_lpm/rte_lpm_neon.h > F: lib/librte_hash/rte*_arm64.h > +F: lib/librte_net/net_crc_neon.h > F: drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c > F: drivers/net/i40e/i40e_rxtx_vec_neon.c > F: drivers/net/virtio/virtio_rxtx_simple_neon.c > diff --git a/lib/librte_eal/common/include/arch/arm/rte_vect.h b/lib/librte_eal/common/include/arch/arm/rte_vect.h > index 4107c99..b215cc9 100644 > --- a/lib/librte_eal/common/include/arch/arm/rte_vect.h > +++ b/lib/librte_eal/common/include/arch/arm/rte_vect.h > @@ -35,6 +35,7 @@ > > #include > #include "generic/rte_vect.h" > +#include "rte_debug.h" > #include "arm_neon.h" > > #ifdef __cplusplus > @@ -78,6 +79,33 @@ vqtbl1q_u8(uint8x16_t a, uint8x16_t b) > } > #endif > > +#if (GCC_VERSION < 70000) > +/* NEON intrinsic vreinterpretq_u64_p128() is supported since GCC version 7 */ > +static inline uint64x2_t > +vreinterpretq_u64_p128(poly128_t x) > +{ > + return (uint64x2_t)x; > +} > + > +/* NEON intrinsic vreinterpretq_p64_u64() is supported since GCC version 7 */ > +static inline poly64x2_t > +vreinterpretq_p64_u64(uint64x2_t x) > +{ > + return (poly64x2_t)x; > +} > + > +/* NEON intrinsic vgetq_lane_p64() is supported since GCC version 7 */ > +static inline poly64_t > +vgetq_lane_p64(poly64x2_t x, const int lane) > +{ > + RTE_ASSERT(lane >= 0 && lane <= 1); > + > + poly64_t *p = (poly64_t *)&x; > + > + return p[lane]; > +} > +#endif > + > #ifdef __cplusplus > } > #endif > diff --git a/lib/librte_net/net_crc_neon.h b/lib/librte_net/net_crc_neon.h > new file mode 100644 > index 0000000..05120a7 > --- /dev/null > +++ b/lib/librte_net/net_crc_neon.h > @@ -0,0 +1,357 @@ > +/* > + * BSD LICENSE > + * > + * Copyright (C) Cavium networks Ltd. 2017. > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions > + * are met: > + * > + * * Redistributions of source code must retain the above copyright > + * notice, this list of conditions and the following disclaimer. > + * * Redistributions in binary form must reproduce the above copyright > + * notice, this list of conditions and the following disclaimer in > + * the documentation and/or other materials provided with the > + * distribution. > + * * Neither the name of Cavium networks nor the names of its > + * contributors may be used to endorse or promote products derived > + * from this software without specific prior written permission. > + * > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS > + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT > + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR > + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT > + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, > + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT > + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, > + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY > + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE > + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + */ > + > +#ifndef _NET_CRC_NEON_H_ > +#define _NET_CRC_NEON_H_ > + > +#include > +#include > +#include > +#include > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/** PMULL CRC computation context structure */ > +struct crc_pmull_ctx { > + uint64x2_t rk1_rk2; > + uint64x2_t rk5_rk6; > + uint64x2_t rk7_rk8; > +}; > + > +struct crc_pmull_ctx crc32_eth_pmull __rte_aligned(16); > +struct crc_pmull_ctx crc16_ccitt_pmull __rte_aligned(16); > + > +static inline uint8x16_t > +extract_vector(uint8x16_t v0, uint8x16_t v1, const int n) > +{ > + switch (n) { > + case 0: return vextq_u8(v0, v1, 0); > + case 1: return vextq_u8(v0, v1, 1); > + case 2: return vextq_u8(v0, v1, 2); > + case 3: return vextq_u8(v0, v1, 3); > + case 4: return vextq_u8(v0, v1, 4); > + case 5: return vextq_u8(v0, v1, 5); > + case 6: return vextq_u8(v0, v1, 6); > + case 7: return vextq_u8(v0, v1, 7); > + case 8: return vextq_u8(v0, v1, 8); > + case 9: return vextq_u8(v0, v1, 9); > + case 10: return vextq_u8(v0, v1, 10); > + case 11: return vextq_u8(v0, v1, 11); > + case 12: return vextq_u8(v0, v1, 12); > + case 13: return vextq_u8(v0, v1, 13); > + case 14: return vextq_u8(v0, v1, 14); > + case 15: return vextq_u8(v0, v1, 15); > + } > + return v1; > +} > + > +/** > + * Shifts right 128 bit register by specified number of bytes > + * > + * @param reg 128 bit value > + * @param num number of bytes to shift reg by (0-16) > + * > + * @return reg << (num * 8) > + */ > +static inline uint64x2_t > +shift_bytes_right(uint64x2_t reg, const unsigned int num) > +{ > + /* Right Shift */ > + return vreinterpretq_u64_u8(extract_vector( > + vreinterpretq_u8_u64(reg), > + vdupq_n_u8(0), > + num)); > +} > + > +/** > + * Shifts left 128 bit register by specified number of bytes > + * > + * @param reg 128 bit value > + * @param num number of bytes to shift reg by (0-16) > + * > + * @return reg << (num * 8) > + */ > +static inline uint64x2_t > +shift_bytes_left(uint64x2_t reg, const unsigned int num) > +{ > + /* Left Shift */ > + return vreinterpretq_u64_u8(extract_vector( > + vdupq_n_u8(0), > + vreinterpretq_u8_u64(reg), > + 16 - num)); > +} > + Can you move shift_bytes_right/shift_bytes_left to rte_vect.h because they are common functions?