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From: Jianbo Liu <jianbo.liu@linaro.org>
Date: Fri, 12 May 2017 16:49:35 +0800
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To: "Sekhar, Ashwin" <Ashwin.Sekhar@cavium.com>
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"jasvinder.singh@intel.com" <jasvinder.singh@intel.com>,
"cristian.dumitrescu@intel.com" <cristian.dumitrescu@intel.com>,
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"Jacob, Jerin" <Jerin.JacobKollanukkaran@cavium.com>,
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Subject: Re: [dpdk-dev] [PATCH v4 3/4] net: add arm64 neon version of CRC
compute APIs
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On 12 May 2017 at 15:25, Sekhar, Ashwin <Ashwin.Sekhar@cavium.com> wrote:
> On Fri, 2017-05-12 at 13:51 +0800, Jianbo Liu wrote:
>> On 9 May 2017 at 17:53, Ashwin Sekhar T K
>> <ashwin.sekhar@caviumnetworks.com> wrote:
>> >
>> > Added CRC compute APIs for arm64 utilizing the pmull
>> > capability
>> >
>> > Added new file net_crc_neon.h to hold the arm64 pmull
>> > CRC implementation
>> >
>> > Verified the changes with crc_autotest unit test case
>> >
>> > Signed-off-by: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
>> > ---
>> > v2:
>> > * Fixed merge conflict in MAINTAINERS
>> >
>> > v3:
>> > * Moved feature detection changes and GCC_VERSION definition
>> > changes to separate commit
>> > * Replaced usage of assert() with RTE_ASSERT()
>> > * Made the comments in rte_vect.h more positive in sense
>> >
>> > v4:
>> > * Rebased on top of latest commit
>> >
>> > MAINTAINERS | 1 +
>> > lib/librte_eal/common/include/arch/arm/rte_vect.h | 28 ++
>> > lib/librte_net/net_crc_neon.h | 357
>> > ++++++++++++++++++++++
>> > lib/librte_net/rte_net_crc.c | 34 ++-
>> > lib/librte_net/rte_net_crc.h | 2 +
>> > 5 files changed, 416 insertions(+), 6 deletions(-)
>> > create mode 100644 lib/librte_net/net_crc_neon.h
>> >
>> >
> ...
>> > +
>> > +struct crc_pmull_ctx crc32_eth_pmull __rte_aligned(16);
>> > +struct crc_pmull_ctx crc16_ccitt_pmull __rte_aligned(16);
>> > +
>> > +static inline uint8x16_t
>> > +extract_vector(uint8x16_t v0, uint8x16_t v1, const int n)
>> > +{
>> > + switch (n) {
>> > + case 0: return vextq_u8(v0, v1, 0);
>> > + case 1: return vextq_u8(v0, v1, 1);
>> > + case 2: return vextq_u8(v0, v1, 2);
>> > + case 3: return vextq_u8(v0, v1, 3);
>> > + case 4: return vextq_u8(v0, v1, 4);
>> > + case 5: return vextq_u8(v0, v1, 5);
>> > + case 6: return vextq_u8(v0, v1, 6);
>> > + case 7: return vextq_u8(v0, v1, 7);
>> > + case 8: return vextq_u8(v0, v1, 8);
>> > + case 9: return vextq_u8(v0, v1, 9);
>> > + case 10: return vextq_u8(v0, v1, 10);
>> > + case 11: return vextq_u8(v0, v1, 11);
>> > + case 12: return vextq_u8(v0, v1, 12);
>> > + case 13: return vextq_u8(v0, v1, 13);
>> > + case 14: return vextq_u8(v0, v1, 14);
>> > + case 15: return vextq_u8(v0, v1, 15);
>> > + }
>> > + return v1;
>> > +}
>> > +
>> > +/**
>> > + * Shifts right 128 bit register by specified number of bytes
>> > + *
>> > + * @param reg 128 bit value
>> > + * @param num number of bytes to shift reg by (0-16)
>> > + *
>> > + * @return reg << (num * 8)
>> > + */
>> > +static inline uint64x2_t
>> > +shift_bytes_right(uint64x2_t reg, const unsigned int num)
>> > +{
>> > + /* Right Shift */
>> > + return vreinterpretq_u64_u8(extract_vector(
>> > + vreinterpretq_u8_u64(reg),
>> > + vdupq_n_u8(0),
>> > + num));
>> > +}
>> > +
>> > +/**
>> > + * Shifts left 128 bit register by specified number of bytes
>> > + *
>> > + * @param reg 128 bit value
>> > + * @param num number of bytes to shift reg by (0-16)
>> > + *
>> > + * @return reg << (num * 8)
>> > + */
>> > +static inline uint64x2_t
>> > +shift_bytes_left(uint64x2_t reg, const unsigned int num)
>> > +{
>> > + /* Left Shift */
>> > + return vreinterpretq_u64_u8(extract_vector(
>> > + vdupq_n_u8(0),
>> > + vreinterpretq_u8_u64(reg),
>> > + 16 - num));
>> > +}
>> > +
>> Can you move shift_bytes_right/shift_bytes_left to rte_vect.h because
>> they are common functions?
> These are not really common functions. I dont think it will have a
> wider usage as its shifting by bytes and not by bits.
>
I think these shifting may be used by other functions.
For example, to replace _mm_srli_si128.
> In x86 case also, xmm_shift_left is not made a common function.
>
But its counterpart right shifting (_mm_srli_si128) is...
> Moreover, I have not tested the behaviour of these functions when the
> shift amt is (< 0) or (> 16) as these cases will never arise in the CRC
> code.
>
You can define thee functions according to current requirement.
And I don't think this parameter can be <0 or > 16.