From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw0-f173.google.com (mail-yw0-f173.google.com [209.85.161.173]) by dpdk.org (Postfix) with ESMTP id 1D302106A for ; Fri, 12 May 2017 10:49:36 +0200 (CEST) Received: by mail-yw0-f173.google.com with SMTP id 203so7954146ywe.0 for ; Fri, 12 May 2017 01:49:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=00qqok2h/d+EPesYkRLDxV7I/xwCF0u+1Twd+zubXTI=; b=iFy3gD8r1JVNLiDBtIqzmmOuIowUnX1Q8N/MzmPsGZNcyLVcZ638lVMY8LaxPepC3u DUuRAdJ+OVL2LG+5GXBnOSPvykmnqiB587OtaofaYDNKlHA573sO6X+nPmZfBOoeq0Fx iMSYbJi3IMigTlcab4SMcepG58f0iiD15jPPI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=00qqok2h/d+EPesYkRLDxV7I/xwCF0u+1Twd+zubXTI=; b=qw0fLA8XtlxFiMLypL7qJQ4TRZ9YrHv/PYVL7IdCotZ6kEdUgZUIsBtbdzNrBETt2K 9m5uyg8a9WE1Mdo/rAQB9FoZ9nf4sHCJ6k8GZx9+BTVCv5nFxRcEY8YTrk6vporHBfB8 UYA18FhGAlD/At0t4ozho+2uSXOt8M1JuVPPbuE9Te2uF/pqoB+04lzUSViQKZsmoAF7 qKgff7UwfqFmo7Ub/of6QA3cbiWa0WVCQTOKZCgeqFAiVA4ii2NjL2tKeQY0ZywPMgz4 GsgH9+55U7byPeIt44OwqHho2OkbMEEX978JAnaAJjnqtY/4h7BgT7HMtcd+Bq6I8lEp QWyQ== X-Gm-Message-State: AODbwcCVsJoFEJpquXH82gPwgRyyeRBIGoeGjkHwBXjDRO3JCGLcjwz5 IpkclGfkCYnHaSL6vIAgMQtTVFaEambr X-Received: by 10.129.173.74 with SMTP id l10mr2140875ywk.114.1494578976111; Fri, 12 May 2017 01:49:36 -0700 (PDT) MIME-Version: 1.0 Received: by 10.37.4.16 with HTTP; Fri, 12 May 2017 01:49:35 -0700 (PDT) In-Reply-To: <1494573934.13572.14.camel@caviumnetworks.com> References: <20170427140618.35897-1-ashwin.sekhar@caviumnetworks.com> <20170509095341.10734-1-ashwin.sekhar@caviumnetworks.com> <20170509095341.10734-3-ashwin.sekhar@caviumnetworks.com> <1494573934.13572.14.camel@caviumnetworks.com> From: Jianbo Liu Date: Fri, 12 May 2017 16:49:35 +0800 Message-ID: To: "Sekhar, Ashwin" Cc: "thomas@monjalon.net" , "jasvinder.singh@intel.com" , "cristian.dumitrescu@intel.com" , "viktorin@rehivetech.com" , "Jacob, Jerin" , "dev@dpdk.org" Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v4 3/4] net: add arm64 neon version of CRC compute APIs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 May 2017 08:49:37 -0000 On 12 May 2017 at 15:25, Sekhar, Ashwin wrote: > On Fri, 2017-05-12 at 13:51 +0800, Jianbo Liu wrote: >> On 9 May 2017 at 17:53, Ashwin Sekhar T K >> wrote: >> > >> > Added CRC compute APIs for arm64 utilizing the pmull >> > capability >> > >> > Added new file net_crc_neon.h to hold the arm64 pmull >> > CRC implementation >> > >> > Verified the changes with crc_autotest unit test case >> > >> > Signed-off-by: Ashwin Sekhar T K >> > --- >> > v2: >> > * Fixed merge conflict in MAINTAINERS >> > >> > v3: >> > * Moved feature detection changes and GCC_VERSION definition >> > changes to separate commit >> > * Replaced usage of assert() with RTE_ASSERT() >> > * Made the comments in rte_vect.h more positive in sense >> > >> > v4: >> > * Rebased on top of latest commit >> > >> > MAINTAINERS | 1 + >> > lib/librte_eal/common/include/arch/arm/rte_vect.h | 28 ++ >> > lib/librte_net/net_crc_neon.h | 357 >> > ++++++++++++++++++++++ >> > lib/librte_net/rte_net_crc.c | 34 ++- >> > lib/librte_net/rte_net_crc.h | 2 + >> > 5 files changed, 416 insertions(+), 6 deletions(-) >> > create mode 100644 lib/librte_net/net_crc_neon.h >> > >> > > ... >> > + >> > +struct crc_pmull_ctx crc32_eth_pmull __rte_aligned(16); >> > +struct crc_pmull_ctx crc16_ccitt_pmull __rte_aligned(16); >> > + >> > +static inline uint8x16_t >> > +extract_vector(uint8x16_t v0, uint8x16_t v1, const int n) >> > +{ >> > + switch (n) { >> > + case 0: return vextq_u8(v0, v1, 0); >> > + case 1: return vextq_u8(v0, v1, 1); >> > + case 2: return vextq_u8(v0, v1, 2); >> > + case 3: return vextq_u8(v0, v1, 3); >> > + case 4: return vextq_u8(v0, v1, 4); >> > + case 5: return vextq_u8(v0, v1, 5); >> > + case 6: return vextq_u8(v0, v1, 6); >> > + case 7: return vextq_u8(v0, v1, 7); >> > + case 8: return vextq_u8(v0, v1, 8); >> > + case 9: return vextq_u8(v0, v1, 9); >> > + case 10: return vextq_u8(v0, v1, 10); >> > + case 11: return vextq_u8(v0, v1, 11); >> > + case 12: return vextq_u8(v0, v1, 12); >> > + case 13: return vextq_u8(v0, v1, 13); >> > + case 14: return vextq_u8(v0, v1, 14); >> > + case 15: return vextq_u8(v0, v1, 15); >> > + } >> > + return v1; >> > +} >> > + >> > +/** >> > + * Shifts right 128 bit register by specified number of bytes >> > + * >> > + * @param reg 128 bit value >> > + * @param num number of bytes to shift reg by (0-16) >> > + * >> > + * @return reg << (num * 8) >> > + */ >> > +static inline uint64x2_t >> > +shift_bytes_right(uint64x2_t reg, const unsigned int num) >> > +{ >> > + /* Right Shift */ >> > + return vreinterpretq_u64_u8(extract_vector( >> > + vreinterpretq_u8_u64(reg), >> > + vdupq_n_u8(0), >> > + num)); >> > +} >> > + >> > +/** >> > + * Shifts left 128 bit register by specified number of bytes >> > + * >> > + * @param reg 128 bit value >> > + * @param num number of bytes to shift reg by (0-16) >> > + * >> > + * @return reg << (num * 8) >> > + */ >> > +static inline uint64x2_t >> > +shift_bytes_left(uint64x2_t reg, const unsigned int num) >> > +{ >> > + /* Left Shift */ >> > + return vreinterpretq_u64_u8(extract_vector( >> > + vdupq_n_u8(0), >> > + vreinterpretq_u8_u64(reg), >> > + 16 - num)); >> > +} >> > + >> Can you move shift_bytes_right/shift_bytes_left to rte_vect.h because >> they are common functions? > These are not really common functions. I dont think it will have a > wider usage as its shifting by bytes and not by bits. > I think these shifting may be used by other functions. For example, to replace _mm_srli_si128. > In x86 case also, xmm_shift_left is not made a common function. > But its counterpart right shifting (_mm_srli_si128) is... > Moreover, I have not tested the behaviour of these functions when the > shift amt is (< 0) or (> 16) as these cases will never arise in the CRC > code. > You can define thee functions according to current requirement. And I don't think this parameter can be <0 or > 16.