From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <jianbo.liu@linaro.org> Received: from mail-yw0-f175.google.com (mail-yw0-f175.google.com [209.85.161.175]) by dpdk.org (Postfix) with ESMTP id C702A2C18 for <dev@dpdk.org>; Fri, 28 Apr 2017 04:14:12 +0200 (CEST) Received: by mail-yw0-f175.google.com with SMTP id k11so24722076ywb.1 for <dev@dpdk.org>; Thu, 27 Apr 2017 19:14:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=U5JHGwHMtfOVGi3IoD7YwxAbwgef/fJmrzNv/11F/1U=; b=kfZvWVPAyQaZk07H2dSriZ/XQE/a6aAa7A8WtxTmg+2ODnweSaWWnnVzzI0cZuRmqP 49M7tPUI7L1hW0aEsD6sKIlO/x+zesIcIwhZNnX+36m4gmu91gPN1dKT2y2N2T8VNNQy uv3HHazPVkRRPhfMywPr7Uy6RWqumDx6GcMIM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=U5JHGwHMtfOVGi3IoD7YwxAbwgef/fJmrzNv/11F/1U=; b=bX3q0+QF5lYSMAGIKpEGg1b8YAQeiZI/k2K9J2jdo2WwZKk8oiqsmRWK5gcgWiC2tn ifqiX5/0/Izd2V0bW+ddvoadaYuk3ItIr6Wv1Cg3X0KgU7b8utKfhZfMUnKwYTTJ+rEe ISyZWuyCKPfFx9CqABryi19Ne6VPIYfcEguFjAmGRcrxIJG6sGHqKbclB8vQv/ZunNWk 5rhzcsVhDE3i+U6o1zR9f1sTQEBrUiCxkmRfPv543QZscxF9K8760HffMlluThlH8k91 JWkKjUBKDZwq/TtlLPPU2w89e2muQBKg4jiVKDklvf8VihiIL5kQmgYoKh6hjMx8hIv0 czXg== X-Gm-Message-State: AN3rC/7b2ZGMXjtmZoDtdU5WHSCQOMeHBEa9PIqdl/15GyGLa1867USr qQUu09nNuCFzK7+qgT1LEA32IHJb+iQ1aMFDRg== X-Received: by 10.129.4.134 with SMTP id 128mr7092961ywe.109.1493345652161; Thu, 27 Apr 2017 19:14:12 -0700 (PDT) MIME-Version: 1.0 Received: by 10.37.4.16 with HTTP; Thu, 27 Apr 2017 19:14:11 -0700 (PDT) In-Reply-To: <20170426162919.15397-1-jerin.jacob@caviumnetworks.com> References: <20170426162919.15397-1-jerin.jacob@caviumnetworks.com> From: Jianbo Liu <jianbo.liu@linaro.org> Date: Fri, 28 Apr 2017 10:14:11 +0800 Message-ID: <CAP4Qi39OGHq8fhmFDqQBsSuU8=w5Trsb0R-=tcJm2GNgKEGcig@mail.gmail.com> To: Jerin Jacob <jerin.jacob@caviumnetworks.com> Cc: dev@dpdk.org, thomas@monjalon.net, Hemant Agrawal <hemant.agrawal@nxp.com>, christian.ehrhardt@canonical.com Content-Type: text/plain; charset=UTF-8 Subject: Re: [dpdk-dev] [PATCH] config: set cache line as 128B in the generic arm64 config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <http://dpdk.org/ml/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://dpdk.org/ml/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <http://dpdk.org/ml/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> X-List-Received-Date: Fri, 28 Apr 2017 02:14:13 -0000 On 27 April 2017 at 00:29, Jerin Jacob <jerin.jacob@caviumnetworks.com> wrote: > armv8 implementations may have 64B or 128B cache line. > Setting to the maximum available cache line size in generic config to > address minimum DMA alignment across all arm64 implementations. > > Increasing the cacheline size has no negative impact to cache invalidation > on systems with a smaller cache line. > > The need for the minimum DMA alignment has impact on functional aspects > of the platform so default config should cater the functional aspects. > > There is an impact on memory usage with this scheme, but that's not too > important for the single image arm64 distribution use case. > > The arm64 linux kernel followed the similar approach for single > arm64 image use case. > http://lxr.free-electrons.com/source/arch/arm64/include/asm/cache.h > > Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> > --- > config/defconfig_arm64-armv8a-linuxapp-gcc | 5 +++++ > config/defconfig_arm64-dpaa2-linuxapp-gcc | 1 + > config/defconfig_arm64-xgene1-linuxapp-gcc | 1 + > 3 files changed, 7 insertions(+) > > diff --git a/config/defconfig_arm64-armv8a-linuxapp-gcc b/config/defconfig_arm64-armv8a-linuxapp-gcc > index 65888cef1..0faa2d3a3 100644 > --- a/config/defconfig_arm64-armv8a-linuxapp-gcc > +++ b/config/defconfig_arm64-armv8a-linuxapp-gcc > @@ -42,6 +42,11 @@ CONFIG_RTE_FORCE_INTRINSICS=y > CONFIG_RTE_TOOLCHAIN="gcc" > CONFIG_RTE_TOOLCHAIN_GCC=y > > +#Maximum available cache line size in arm64 implementations. Setting to maximum > +#available cache line size in generic config to address minimum DMA alignment > +#across all arm64 implementations. > +CONFIG_RTE_CACHE_LINE_SIZE=128 > + > CONFIG_RTE_EAL_IGB_UIO=n > > CONFIG_RTE_LIBRTE_FM10K_PMD=n > diff --git a/config/defconfig_arm64-dpaa2-linuxapp-gcc b/config/defconfig_arm64-dpaa2-linuxapp-gcc > index 010cb8092..314a0eceb 100644 > --- a/config/defconfig_arm64-dpaa2-linuxapp-gcc > +++ b/config/defconfig_arm64-dpaa2-linuxapp-gcc > @@ -41,6 +41,7 @@ CONFIG_RTE_ARCH_ARM_TUNE="cortex-a57+fp+simd" > # > CONFIG_RTE_MAX_LCORE=8 > CONFIG_RTE_MAX_NUMA_NODES=1 > +CONFIG_RTE_CACHE_LINE_SIZE=64 > > CONFIG_RTE_PKTMBUF_HEADROOM=256 > > diff --git a/config/defconfig_arm64-xgene1-linuxapp-gcc b/config/defconfig_arm64-xgene1-linuxapp-gcc > index f096166b7..d8e544728 100644 > --- a/config/defconfig_arm64-xgene1-linuxapp-gcc > +++ b/config/defconfig_arm64-xgene1-linuxapp-gcc > @@ -32,3 +32,4 @@ > #include "defconfig_arm64-armv8a-linuxapp-gcc" > > CONFIG_RTE_MACHINE="xgene1" > +CONFIG_RTE_CACHE_LINE_SIZE=64 > -- Acked-by: Jianbo Liu <jianbo.liu@linaro.org>