From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw0-f178.google.com (mail-yw0-f178.google.com [209.85.161.178]) by dpdk.org (Postfix) with ESMTP id 66A1A29AC for ; Fri, 19 May 2017 03:46:41 +0200 (CEST) Received: by mail-yw0-f178.google.com with SMTP id l14so29032574ywk.1 for ; Thu, 18 May 2017 18:46:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=3huvSkUfTeCPCICQMSq4kk8JDnvvbAc/yGGcO+Jp/UA=; b=PiHYS7q3i2odaN7U+W/WPN1YunVnyTQA4ZJQ2Qp7AbcVeupPT2L6IFniPy3w9FDuzt GpLO/HezVrmYo8B6ojWepWO41REzX4ah8NEuCJbCNmdeuh6g+mHhF1f6Y5SdEIt8TxNO 64sUse5Od6MudQJWoXJrSjrs3nRDj9tweyXSk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=3huvSkUfTeCPCICQMSq4kk8JDnvvbAc/yGGcO+Jp/UA=; b=GcW48hWqqNdt5kJqSE4On/8sN/Nw9JEyYvqnB8i9l1vv1Z6/JgDBIq0KmOdwWwbeKX uD7BozA75XtP9AoCVUyZn0uPeQ8TClLD1nAYkGo4W/CQaxfxmFun7INilQ63O2JUHd8H lfzRFYHcoaPWFC/vj0c5rhELAlSOIpKxDMRgnadZRDpPYhslpSQC5ktPhb1y7CjQEHSQ VmwnR7VVmimS72h5K9junUOSZPB54v/KoznqEcRsPQ/fdDrHdej0leKZ6gfmLU5HcqRE 2Ws/A+mpCWc81KNDQ8ZfhqWXQz4AANn2+lJk+kPsLPLA5n0fsGrgu3lw2AoBiRPILHu5 6Zzg== X-Gm-Message-State: AODbwcDlGbuH+kyI879jakn35ZXAJHSULNfnQZgYNDD4O5SEUa9lMvuY lIKzx9RRX/kr/gLcyhuDNeqwZG5+WnJm X-Received: by 10.13.242.71 with SMTP id b68mr5933206ywf.292.1495158400748; Thu, 18 May 2017 18:46:40 -0700 (PDT) MIME-Version: 1.0 Received: by 10.37.4.16 with HTTP; Thu, 18 May 2017 18:46:40 -0700 (PDT) In-Reply-To: <20170518101657.GA17993@jerin> References: <20170511101046.26456-1-jerin.jacob@caviumnetworks.com> <20170511101046.26456-3-jerin.jacob@caviumnetworks.com> <20170518101657.GA17993@jerin> From: Jianbo Liu Date: Fri, 19 May 2017 09:46:40 +0800 Message-ID: To: Jerin Jacob Cc: dev@dpdk.org, thomas@monjalon.net, Jan Viktorin Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH 3/6] eal/arm64: rte pause implementation for arm64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 19 May 2017 01:46:41 -0000 On 18 May 2017 at 18:16, Jerin Jacob wrote: > -----Original Message----- >> Date: Thu, 18 May 2017 17:40:58 +0800 >> From: Jianbo Liu >> To: Jerin Jacob >> Cc: dev@dpdk.org, thomas@monjalon.net, Jan Viktorin >> >> Subject: Re: [dpdk-dev] [PATCH 3/6] eal/arm64: rte pause implementation for >> arm64 >> >> On 11 May 2017 at 18:10, Jerin Jacob wrote: >> > CC: Jianbo Liu >> > Signed-off-by: Jerin Jacob >> > --- >> > lib/librte_eal/common/include/arch/arm/rte_pause.h | 4 ++ >> > .../common/include/arch/arm/rte_pause_64.h | 55 ++++++++++++++++++++++ >> > 2 files changed, 59 insertions(+) >> > create mode 100644 lib/librte_eal/common/include/arch/arm/rte_pause_64.h >> > >> > diff --git a/lib/librte_eal/common/include/arch/arm/rte_pause.h b/lib/librte_eal/common/include/arch/arm/rte_pause.h >> > index 0fe88aba9..9b79405e6 100644 >> > --- a/lib/librte_eal/common/include/arch/arm/rte_pause.h >> > +++ b/lib/librte_eal/common/include/arch/arm/rte_pause.h >> > @@ -37,7 +37,11 @@ >> > extern "C" { >> > #endif >> > >> > +#ifdef RTE_ARCH_64 >> > +#include >> > +#else >> > #include >> > +#endif >> > >> > #ifdef __cplusplus >> > } >> > diff --git a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h >> > new file mode 100644 >> > index 000000000..cae996de8 >> > --- /dev/null >> > +++ b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h >> > @@ -0,0 +1,55 @@ >> > +/* >> > + * BSD LICENSE >> > + * >> > + * Copyright(c) 2017 Cavium. All rights reserved. >> > + * >> > + * Redistribution and use in source and binary forms, with or without >> > + * modification, are permitted provided that the following conditions >> > + * are met: >> > + * >> > + * * Redistributions of source code must retain the above copyright >> > + * notice, this list of conditions and the following disclaimer. >> > + * * Redistributions in binary form must reproduce the above copyright >> > + * notice, this list of conditions and the following disclaimer in >> > + * the documentation and/or other materials provided with the >> > + * distribution. >> > + * * Neither the name of Cavium nor the names of its >> > + * contributors may be used to endorse or promote products derived >> > + * from this software without specific prior written permission. >> > + * >> > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS >> > + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT >> > + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR >> > + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT >> > + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, >> > + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT >> > + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, >> > + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY >> > + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT >> > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE >> > + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >> > + */ >> > + >> > +#ifndef _RTE_PAUSE_ARM64_H_ >> > +#define _RTE_PAUSE_ARM64_H_ >> > + >> > +#ifdef __cplusplus >> > +extern "C" { >> > +#endif >> > + >> > +#include >> > +#include "generic/rte_pause.h" >> > + >> > +static inline void rte_pause(void) >> > +{ >> > + /* YIELD hints the CPU to switch to another thread if possible >> > + * and executes as a NOP otherwise. >> >> I think you can remove the second line if you are trying to explain >> what YIELD instruction is. >> And I wonder if it can save power as rte_thread is bounded to certain >> core and always polling while YIELD is only a hint instruction. > > AFAIK, It is HW thread not software OS thread.ie Simultaneous Multi-Threading (SMT) > or Hyper threading. > I read aarch64 ISA, and thought it's software thread. It's likely each partner can extend more on its own implementation. > For example, Cavium 99xx has 4 HW threads per physical core. > > I agree on comment. I think, I can remove the comment as YIELD is just a hint > and varies based on arm64 implementation. Will fix it v2. > OK >> >> > + */ >> > + asm volatile("yield" ::: "memory"); >> > +} >> > + >> > +#ifdef __cplusplus >> > +} >> > +#endif >> > + >> > +#endif /* _RTE_PAUSE_ARM64_H_ */ >> > -- >> > 2.12.2 >> >