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Mon, 15 Apr 2019 20:40:52 +0000 From: Yongseok Koh To: Honnappa Nagarahalli CC: "jerinj@marvell.com" , "bruce.richardson@intel.com" , Pavan Nikhilesh Bhagavatula , Shahaf Shuler , "dev@dpdk.org" , Thomas Monjalon , "Gavin Hu (Arm Technology China)" , nd Thread-Topic: [EXT] [PATCH 2/6] meson: change default cache line size for cortex-a72 Thread-Index: AQHU8cQ7pmeKHamEcEiBcav9kYOvOKY8pdAAgACYSgCAAHVjAA== Date: Mon, 15 Apr 2019 20:40:51 +0000 Message-ID: References: <20190412232451.30197-1-yskoh@mellanox.com> <20190412232451.30197-3-yskoh@mellanox.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [209.116.155.178] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d4e2ebb1-e20a-49a4-7ab6-08d6c1e2a688 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600140)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); 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charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: d4e2ebb1-e20a-49a4-7ab6-08d6c1e2a688 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Apr 2019 20:40:51.8654 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB4057 Subject: Re: [dpdk-dev] [EXT] [PATCH 2/6] meson: change default cache line size for cortex-a72 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 15 Apr 2019 20:40:54 -0000 > On Apr 15, 2019, at 6:40 AM, Honnappa Nagarahalli wrote: >=20 >>=20 >>>>=20 >>>> -------------------------------------------------------------------- >>>> -- Per the email discussion [1], the default cache line size of >>>> armv8 >>>> cortex-a72 is changed to 64 bytes. >>>=20 >>> IMO, In git commit you remove the reference to specific discussion and >>> Update the reason correctly. >>>=20 >>>=20 >>>>=20 >>>> [1] https://eur03.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%= 2Fmails.dpdk.org%2Farchives%2Fdev%2F2019-January%2F123218.html&data=3D0= 2%7C01%7Cyskoh%40mellanox.com%7C4c0cdd9535c84c8dd3c008d6c1a7f5eb%7Ca652971c= 7d2e4d9ba6a4d149256f461b%7C0%7C0%7C636909324474698429&sdata=3DUJO2lBtnY= WSs5ud8CsAL7oGXH571f6zGjrVmP2SRChw%3D&reserved=3D0 >>>>=20 >>>> Signed-off-by: Yongseok Koh >>>> --- >>>> config/arm/meson.build | 4 +++- >>>> 1 file changed, 3 insertions(+), 1 deletion(-) >>>>=20 >>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index >>>> e00b894523..73c581948c 100644 >>>> --- a/config/arm/meson.build >>>> +++ b/config/arm/meson.build >>>> @@ -51,6 +51,8 @@ flags_dpaa2 =3D [ >>>> ['RTE_MAX_LCORE', 16], >>>> ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] flags_default_extra >>> =3D [] >>>> +flags_cortex_a72_extra =3D [ >>>> + ['RTE_CACHE_LINE_SIZE', 64]] >>>> flags_thunderx_extra =3D [ >> Which tree does this patch apply to? I do not see the above line in mast= er. > Please ignore this comment, I missed the dependency provided in 0/6 >=20 >>=20 >>>> ['RTE_MACHINE', '"thunderx"'], >>>> ['RTE_USE_C11_MEM_MODEL', false]] >>>> @@ -73,7 +75,7 @@ machine_args_generic =3D [ >>>> ['0xd03', ['-mcpu=3Dcortex-a53']], >>>> ['0xd04', ['-mcpu=3Dcortex-a35']], >>>> ['0xd07', ['-mcpu=3Dcortex-a57']], >>>> - ['0xd08', ['-mcpu=3Dcortex-a72']], >>>> + ['0xd08', ['-mcpu=3Dcortex-a72'], flags_cortex_a72_extra], >>>> ['0xd09', ['-mcpu=3Dcortex-a73']], >>>> ['0xd0a', ['-mcpu=3Dcortex-a75']]] >>>=20 >>> I think, flags_cortex_a72_extra() can be changed to >>> flags_vendor_arm_extra or something similar And update the following >>> CPUs also not just cortex-a72. >>>=20 >> Why not add 'flags_arm' similar to flags_dpaa2/flag_cavium etc? All the >> listed Arm cores are 64B cache line size. If so, I'd take your approach - flags_arm. If we have an exception (CL size is 128 for some cpu) someday, then we can add an extra flag for that. > Just to complete the thought, impl_0x41 can use 'flags_arm' instead of 'f= lags_generic'. IMO, current use of 'flags_generic' in impl_0x41 is incorrec= t. >=20 >>=20 >>> ['0xd03', ['-mcpu=3Dcortex-a53']], >>> ['0xd04', ['-mcpu=3Dcortex-a35']], >>> ['0xd05', ['-mcpu=3Dcortex-a55']], >>> ['0xd07', ['-mcpu=3Dcortex-a57']], >>> ['0xd08', ['-mcpu=3Dcortex-a72']], >>> ['0xd09', ['-mcpu=3Dcortex-a73']], >>> ['0xd0a', ['-mcpu=3Dcortex-a75']], >>> ['0xd0b', ['-mcpu=3Dcortex-a76']], >>>=20 >>>=20 >>>>=20 >>>> -- >>>> 2.21.0.196.g041f5ea >=20 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 5B6CDA00E6 for ; Mon, 15 Apr 2019 22:40:55 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0DB0D1B3B8; Mon, 15 Apr 2019 22:40:55 +0200 (CEST) Received: from EUR01-DB5-obe.outbound.protection.outlook.com (mail-eopbgr150078.outbound.protection.outlook.com [40.107.15.78]) by dpdk.org (Postfix) with ESMTP id D28BF1B202 for ; Mon, 15 Apr 2019 22:40:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NzZr5D6KzaykxJZuqYle/JHdlmz8H68LfZXMPl2ml5Q=; b=xm5kHRim5J/TMiGXpTReebgPiMmhHBIq5FAcHqruwUPNezNad426wnvzGNyvlWZEmHoJ0LPOj+GshEZHUQNUi80wdBGWdmX+2QXlZ4t8QUbN2Y/v1GOZljwcd7QobDCcsVv3UFUuQnfPyoBr5yiiarWqH8uRChyawuvUsOY19tg= Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com (52.134.72.27) by DB3PR0502MB4057.eurprd05.prod.outlook.com (52.134.67.18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1792.17; Mon, 15 Apr 2019 20:40:52 +0000 Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a]) by DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a%3]) with mapi id 15.20.1792.018; Mon, 15 Apr 2019 20:40:52 +0000 From: Yongseok Koh To: Honnappa Nagarahalli CC: "jerinj@marvell.com" , "bruce.richardson@intel.com" , Pavan Nikhilesh Bhagavatula , Shahaf Shuler , "dev@dpdk.org" , Thomas Monjalon , "Gavin Hu (Arm Technology China)" , nd Thread-Topic: [EXT] [PATCH 2/6] meson: change default cache line size for cortex-a72 Thread-Index: AQHU8cQ7pmeKHamEcEiBcav9kYOvOKY8pdAAgACYSgCAAHVjAA== Date: Mon, 15 Apr 2019 20:40:51 +0000 Message-ID: References: <20190412232451.30197-1-yskoh@mellanox.com> <20190412232451.30197-3-yskoh@mellanox.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0502MB4057; H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: FdFH8tf1m0Ffct9/wLy5MfHrseCbM7PjiYRrgoJhijrfR9MFz601PGcwRuRzk0kGZgPI1vX8W8/r+rh9gyh0r2ss+Ya64LtVM7E8UqirRQQ6NpL9onNT06sxXxBjpf1DGHZA/fZdtWsWX+X+/7BaLJkfH25ZK8+CzETKt3FkiY6g+srPSlUZKvXH33N7F5AS9KJqY7nWfk9ozgVADHxaWEat5SvE1hp7NN4OYpOiw5l6ndcxkZSxfii0kJqYsUONb+P+zxu3C9EgwPQ+NPRtbLjPhX7HrLWZ0hNaSrkpsjIklxR7RKPFI+lJ6VuT01UX8qw+YwftBe8uivUkPMhZ5osXCSMMZDOg9rouGZBtjmsMIPBrFOxgiZmrBn++jls/NAH1PxV2G5QmHCkhoT8H9/E0JvXIL/cL78TrM0rmHo4= Content-Type: text/plain; charset="UTF-8" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: d4e2ebb1-e20a-49a4-7ab6-08d6c1e2a688 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Apr 2019 20:40:51.8654 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB4057 Subject: Re: [dpdk-dev] [EXT] [PATCH 2/6] meson: change default cache line size for cortex-a72 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190415204051.QMLViHMY7-kTy3fAr1F4tdy2wlcS6Y0rllTXaC-550o@z> > On Apr 15, 2019, at 6:40 AM, Honnappa Nagarahalli wrote: >=20 >>=20 >>>>=20 >>>> -------------------------------------------------------------------- >>>> -- Per the email discussion [1], the default cache line size of >>>> armv8 >>>> cortex-a72 is changed to 64 bytes. >>>=20 >>> IMO, In git commit you remove the reference to specific discussion and >>> Update the reason correctly. >>>=20 >>>=20 >>>>=20 >>>> [1] https://eur03.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%= 2Fmails.dpdk.org%2Farchives%2Fdev%2F2019-January%2F123218.html&data=3D0= 2%7C01%7Cyskoh%40mellanox.com%7C4c0cdd9535c84c8dd3c008d6c1a7f5eb%7Ca652971c= 7d2e4d9ba6a4d149256f461b%7C0%7C0%7C636909324474698429&sdata=3DUJO2lBtnY= WSs5ud8CsAL7oGXH571f6zGjrVmP2SRChw%3D&reserved=3D0 >>>>=20 >>>> Signed-off-by: Yongseok Koh >>>> --- >>>> config/arm/meson.build | 4 +++- >>>> 1 file changed, 3 insertions(+), 1 deletion(-) >>>>=20 >>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index >>>> e00b894523..73c581948c 100644 >>>> --- a/config/arm/meson.build >>>> +++ b/config/arm/meson.build >>>> @@ -51,6 +51,8 @@ flags_dpaa2 =3D [ >>>> ['RTE_MAX_LCORE', 16], >>>> ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] flags_default_extra >>> =3D [] >>>> +flags_cortex_a72_extra =3D [ >>>> + ['RTE_CACHE_LINE_SIZE', 64]] >>>> flags_thunderx_extra =3D [ >> Which tree does this patch apply to? I do not see the above line in mast= er. > Please ignore this comment, I missed the dependency provided in 0/6 >=20 >>=20 >>>> ['RTE_MACHINE', '"thunderx"'], >>>> ['RTE_USE_C11_MEM_MODEL', false]] >>>> @@ -73,7 +75,7 @@ machine_args_generic =3D [ >>>> ['0xd03', ['-mcpu=3Dcortex-a53']], >>>> ['0xd04', ['-mcpu=3Dcortex-a35']], >>>> ['0xd07', ['-mcpu=3Dcortex-a57']], >>>> - ['0xd08', ['-mcpu=3Dcortex-a72']], >>>> + ['0xd08', ['-mcpu=3Dcortex-a72'], flags_cortex_a72_extra], >>>> ['0xd09', ['-mcpu=3Dcortex-a73']], >>>> ['0xd0a', ['-mcpu=3Dcortex-a75']]] >>>=20 >>> I think, flags_cortex_a72_extra() can be changed to >>> flags_vendor_arm_extra or something similar And update the following >>> CPUs also not just cortex-a72. >>>=20 >> Why not add 'flags_arm' similar to flags_dpaa2/flag_cavium etc? All the >> listed Arm cores are 64B cache line size. If so, I'd take your approach - flags_arm. If we have an exception (CL size is 128 for some cpu) someday, then we can add an extra flag for that. > Just to complete the thought, impl_0x41 can use 'flags_arm' instead of 'f= lags_generic'. IMO, current use of 'flags_generic' in impl_0x41 is incorrec= t. >=20 >>=20 >>> ['0xd03', ['-mcpu=3Dcortex-a53']], >>> ['0xd04', ['-mcpu=3Dcortex-a35']], >>> ['0xd05', ['-mcpu=3Dcortex-a55']], >>> ['0xd07', ['-mcpu=3Dcortex-a57']], >>> ['0xd08', ['-mcpu=3Dcortex-a72']], >>> ['0xd09', ['-mcpu=3Dcortex-a73']], >>> ['0xd0a', ['-mcpu=3Dcortex-a75']], >>> ['0xd0b', ['-mcpu=3Dcortex-a76']], >>>=20 >>>=20 >>>>=20 >>>> -- >>>> 2.21.0.196.g041f5ea >=20