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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CH3PR11MB8362.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a3337ba8-22e5-4647-4b8c-08dbb8b92e80 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Sep 2023 02:36:09.1319 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: /9Ovqw6p7T4bRA8XY7INyihFjd2qRuc3jExylEwZraHP6REaSar5PfnX6XnJIL2B3SfYOqUELUGSVm9dGkd00g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR11MB7692 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: David Marchand > Sent: Thursday, September 14, 2023 8:36 PM > To: dev@dpdk.org > Cc: thomas@monjalon.net; ferruh.yigit@amd.com; Xia, Chenbo > ; nipun.gupta@amd.com; Richardson, Bruce > ; Sevincer, Abdullah > ; Gaetan Rivet > Subject: [PATCH v3 13/15] pci: define some PRI constants >=20 > Define some PCI PRI extended feature constants and use them in existing > drivers. >=20 > Signed-off-by: David Marchand > Acked-by: Bruce Richardson > --- > drivers/event/dlb2/pf/dlb2_main.c | 11 ++++------- > lib/pci/rte_pci.h | 5 +++++ > 2 files changed, 9 insertions(+), 7 deletions(-) >=20 > diff --git a/drivers/event/dlb2/pf/dlb2_main.c > b/drivers/event/dlb2/pf/dlb2_main.c > index 8e729d1964..187a356c24 100644 > --- a/drivers/event/dlb2/pf/dlb2_main.c > +++ b/drivers/event/dlb2/pf/dlb2_main.c > @@ -27,9 +27,6 @@ > #define NO_OWNER_VF 0 /* PF ONLY! */ > #define NOT_VF_REQ false /* PF ONLY! */ >=20 > -#define DLB2_PCI_PRI_CTRL_ENABLE 0x1 > -#define DLB2_PCI_PRI_ALLOC_REQ 0xC > -#define DLB2_PCI_PRI_CTRL 0x4 > #define DLB2_PCI_ERR_ROOT_STATUS 0x30 > #define DLB2_PCI_ERR_COR_STATUS 0x10 > #define DLB2_PCI_ERR_UNCOR_STATUS 0x4 > @@ -257,7 +254,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) > pri_cap_offset =3D rte_pci_find_ext_capability(pdev, off); >=20 > if (pri_cap_offset >=3D 0) { > - off =3D pri_cap_offset + DLB2_PCI_PRI_ALLOC_REQ; > + off =3D pri_cap_offset + RTE_PCI_PRI_ALLOC_REQ; > if (rte_pci_read_config(pdev, &pri_reqs_dword, 4, off) !=3D 4) > pri_reqs_dword =3D 0; > } > @@ -377,9 +374,9 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) > } >=20 > if (pri_cap_offset >=3D 0) { > - pri_ctrl_word =3D DLB2_PCI_PRI_CTRL_ENABLE; > + pri_ctrl_word =3D RTE_PCI_PRI_CTRL_ENABLE; >=20 > - off =3D pri_cap_offset + DLB2_PCI_PRI_ALLOC_REQ; > + off =3D pri_cap_offset + RTE_PCI_PRI_ALLOC_REQ; > ret =3D rte_pci_write_config(pdev, &pri_reqs_dword, 4, off); > if (ret !=3D 4) { > DLB2_LOG_ERR("[%s()] failed to write the pcie config > space at offset %d\n", > @@ -387,7 +384,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) > return ret; > } >=20 > - off =3D pri_cap_offset + DLB2_PCI_PRI_CTRL; > + off =3D pri_cap_offset + RTE_PCI_PRI_CTRL; > ret =3D rte_pci_write_config(pdev, &pri_ctrl_word, 2, off); > if (ret !=3D 2) { > DLB2_LOG_ERR("[%s()] failed to write the pcie config > space at offset %d\n", > diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h > index a6c52a232d..6bbcad20f2 100644 > --- a/lib/pci/rte_pci.h > +++ b/lib/pci/rte_pci.h > @@ -123,6 +123,11 @@ extern "C" { > #define RTE_PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ > #define RTE_PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ >=20 > +/* Page Request Interface (RTE_PCI_EXT_CAP_ID_PRI) */ > +#define RTE_PCI_PRI_CTRL 0x04 /* PRI control register */ > +#define RTE_PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */ > +#define RTE_PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ > + > /** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */ > #define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8 > #define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X") > -- > 2.41.0 Reviewed-by: Chenbo Xia =20