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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CH3PR11MB8362.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: b8d495dd-4367-4f54-1e96-08dbafa49854 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Sep 2023 13:16:06.7846 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: sqHfdh3G6x58/rf1aeZuYCljUOK1lnJWTVFalCPVZhAqdmm6WsKhW/HHMX2r/VbcEi3+co7TOSmajj9pa8BxhA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR11MB7659 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: David Marchand > Sent: Monday, August 21, 2023 7:36 PM > To: dev@dpdk.org > Cc: thomas@monjalon.net; ferruh.yigit@amd.com; Xia, Chenbo > ; nipun.gupta@amd.com; Richardson, Bruce > ; Burakov, Anatoly ; > Gaetan Rivet > Subject: [PATCH v2 08/15] pci: define some BAR constants >=20 > Define some PCI BAR constants and use them in existing drivers. >=20 > Signed-off-by: David Marchand > Acked-by: Bruce Richardson > --- > drivers/bus/pci/linux/pci_vfio.c | 7 +++---- > lib/pci/rte_pci.h | 4 ++++ > 2 files changed, 7 insertions(+), 4 deletions(-) >=20 > diff --git a/drivers/bus/pci/linux/pci_vfio.c > b/drivers/bus/pci/linux/pci_vfio.c > index bf91492dd9..3f3201daf2 100644 > --- a/drivers/bus/pci/linux/pci_vfio.c > +++ b/drivers/bus/pci/linux/pci_vfio.c > @@ -5,7 +5,6 @@ > #include > #include > #include > -#include > #include > #include > #include > @@ -427,14 +426,14 @@ pci_vfio_is_ioport_bar(const struct rte_pci_device > *dev, int vfio_dev_fd, > } >=20 > ret =3D pread64(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar), > - offset + PCI_BASE_ADDRESS_0 + bar_index * 4); > + offset + RTE_PCI_BASE_ADDRESS_0 + bar_index * 4); > if (ret !=3D sizeof(ioport_bar)) { > RTE_LOG(ERR, EAL, "Cannot read command (%x) from config > space!\n", > - PCI_BASE_ADDRESS_0 + bar_index*4); > + RTE_PCI_BASE_ADDRESS_0 + bar_index*4); > return -1; > } >=20 > - return (ioport_bar & PCI_BASE_ADDRESS_SPACE_IO) !=3D 0; > + return (ioport_bar & RTE_PCI_BASE_ADDRESS_SPACE_IO) !=3D 0; > } >=20 > static int > diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h > index 9eb8f85ceb..62bf87aa10 100644 > --- a/lib/pci/rte_pci.h > +++ b/lib/pci/rte_pci.h > @@ -35,6 +35,7 @@ extern "C" { > #define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */ > #define RTE_PCI_COMMAND 0x04 /* 16 bits */ > #define RTE_PCI_STATUS 0x06 /* 16 bits */ > +#define RTE_PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ > #define RTE_PCI_CAPABILITY_LIST 0x34 /* 32 bits */ >=20 > /* PCI Command Register (RTE_PCI_COMMAND) */ > @@ -45,6 +46,9 @@ extern "C" { > /* PCI Status Register (RTE_PCI_STATUS) */ > #define RTE_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List > */ >=20 > +/* Base addresses (RTE_PCI_BASE_ADDRESS_*) */ > +#define RTE_PCI_BASE_ADDRESS_SPACE_IO 0x01 > + > /* Capability registers (RTE_PCI_CAPABILITY_LIST) */ > #define RTE_PCI_CAP_ID_PM 0x01 /* Power Management */ > #define RTE_PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts > */ > -- > 2.41.0 Reviewed-by: Chenbo Xia =20