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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CH3PR11MB8362.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: b6d2e15a-6dde-4e4a-66be-08dbb8b90cb5 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Sep 2023 02:35:12.4550 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: LyDKzBzoPNCWsnMrWLX1IwAIF8CYLnEFTiXwQKsBZ8tQ/TfYxT+aFS8QfJ31+uStD0Zd/D37umoMDKG4Me7Slg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR11MB7692 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: David Marchand > Sent: Thursday, September 14, 2023 8:36 PM > To: dev@dpdk.org > Cc: thomas@monjalon.net; ferruh.yigit@amd.com; Xia, Chenbo > ; nipun.gupta@amd.com; Richardson, Bruce > ; Sevincer, Abdullah > ; Gaetan Rivet > Subject: [PATCH v3 12/15] pci: define some ACS constants >=20 > Define some PCI ACS extended feature constants and use them in existing > drivers. >=20 > Signed-off-by: David Marchand > Acked-by: Bruce Richardson > --- > drivers/event/dlb2/pf/dlb2_main.c | 23 ++++++++--------------- > lib/pci/rte_pci.h | 9 +++++++++ > 2 files changed, 17 insertions(+), 15 deletions(-) >=20 > diff --git a/drivers/event/dlb2/pf/dlb2_main.c > b/drivers/event/dlb2/pf/dlb2_main.c > index 29e3001627..8e729d1964 100644 > --- a/drivers/event/dlb2/pf/dlb2_main.c > +++ b/drivers/event/dlb2/pf/dlb2_main.c > @@ -33,13 +33,6 @@ > #define DLB2_PCI_ERR_ROOT_STATUS 0x30 > #define DLB2_PCI_ERR_COR_STATUS 0x10 > #define DLB2_PCI_ERR_UNCOR_STATUS 0x4 > -#define DLB2_PCI_ACS_CAP 0x4 > -#define DLB2_PCI_ACS_CTRL 0x6 > -#define DLB2_PCI_ACS_SV 0x1 > -#define DLB2_PCI_ACS_RR 0x4 > -#define DLB2_PCI_ACS_CR 0x8 > -#define DLB2_PCI_ACS_UF 0x10 > -#define DLB2_PCI_ACS_EC 0x20 >=20 > static int > dlb2_pf_init_driver_state(struct dlb2_dev *dlb2_dev) > @@ -492,16 +485,16 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) >=20 > if (acs_cap_offset >=3D 0) { > uint16_t acs_cap, acs_ctrl, acs_mask; > - off =3D acs_cap_offset + DLB2_PCI_ACS_CAP; > + off =3D acs_cap_offset + RTE_PCI_ACS_CAP; > if (rte_pci_read_config(pdev, &acs_cap, 2, off) !=3D 2) > acs_cap =3D 0; >=20 > - off =3D acs_cap_offset + DLB2_PCI_ACS_CTRL; > + off =3D acs_cap_offset + RTE_PCI_ACS_CTRL; > if (rte_pci_read_config(pdev, &acs_ctrl, 2, off) !=3D 2) > acs_ctrl =3D 0; >=20 > - acs_mask =3D DLB2_PCI_ACS_SV | DLB2_PCI_ACS_RR; > - acs_mask |=3D (DLB2_PCI_ACS_CR | DLB2_PCI_ACS_UF); > + acs_mask =3D RTE_PCI_ACS_SV | RTE_PCI_ACS_RR; > + acs_mask |=3D (RTE_PCI_ACS_CR | RTE_PCI_ACS_UF); > acs_ctrl |=3D (acs_cap & acs_mask); >=20 > ret =3D rte_pci_write_config(pdev, &acs_ctrl, 2, off); > @@ -511,15 +504,15 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) > return ret; > } >=20 > - off =3D acs_cap_offset + DLB2_PCI_ACS_CTRL; > + off =3D acs_cap_offset + RTE_PCI_ACS_CTRL; > if (rte_pci_read_config(pdev, &acs_ctrl, 2, off) !=3D 2) > acs_ctrl =3D 0; >=20 > - acs_mask =3D DLB2_PCI_ACS_RR | DLB2_PCI_ACS_CR; > - acs_mask |=3D DLB2_PCI_ACS_EC; > + acs_mask =3D RTE_PCI_ACS_RR | RTE_PCI_ACS_CR; > + acs_mask |=3D RTE_PCI_ACS_EC; > acs_ctrl &=3D ~acs_mask; >=20 > - off =3D acs_cap_offset + DLB2_PCI_ACS_CTRL; > + off =3D acs_cap_offset + RTE_PCI_ACS_CTRL; > ret =3D rte_pci_write_config(pdev, &acs_ctrl, 2, off); > if (ret !=3D 2) { > DLB2_LOG_ERR("[%s()] failed to write the pcie config > space at offset %d\n", > diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h > index 1fdca91f8b..a6c52a232d 100644 > --- a/lib/pci/rte_pci.h > +++ b/lib/pci/rte_pci.h > @@ -102,6 +102,15 @@ extern "C" { > #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV */ > #define RTE_PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface > */ >=20 > +/* Access Control Service (RTE_PCI_EXT_CAP_ID_ACS) */ > +#define RTE_PCI_ACS_CAP 0x04 /* ACS Capability Register > */ > +#define RTE_PCI_ACS_CTRL 0x06 /* ACS Control Register */ > +#define RTE_PCI_ACS_SV 0x0001 /* Source Validation */ > +#define RTE_PCI_ACS_RR 0x0004 /* P2P Request Redirect */ > +#define RTE_PCI_ACS_CR 0x0008 /* P2P Completion Redirect > */ > +#define RTE_PCI_ACS_UF 0x0010 /* Upstream Forwarding */ > +#define RTE_PCI_ACS_EC 0x0020 /* P2P Egress Control */ > + > /* Single Root I/O Virtualization (RTE_PCI_EXT_CAP_ID_SRIOV) */ > #define RTE_PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ > #define RTE_PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ > -- > 2.41.0 Reviewed-by: Chenbo Xia =20