From: "Tummala, Sivaprasad" <Sivaprasad.Tummala@amd.com>
To: Bruce Richardson <bruce.richardson@intel.com>
Cc: "david.hunt@intel.com" <david.hunt@intel.com>,
"honnappa.nagarahalli@arm.com" <honnappa.nagarahalli@arm.com>,
"anatoly.burakov@intel.com" <anatoly.burakov@intel.com>,
"jerinj@marvell.com" <jerinj@marvell.com>,
"radu.nicolau@intel.com" <radu.nicolau@intel.com>,
"gakhil@marvell.com" <gakhil@marvell.com>,
"cristian.dumitrescu@intel.com" <cristian.dumitrescu@intel.com>,
"Yigit, Ferruh" <Ferruh.Yigit@amd.com>,
"konstantin.ananyev@huawei.com" <konstantin.ananyev@huawei.com>,
"dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [PATCH] test/ring_perf: add optional cross L3 core selection
Date: Sat, 18 Oct 2025 04:38:21 +0000 [thread overview]
Message-ID: <CH3PR12MB8233C56EA9E26C5BF20A282686F7A@CH3PR12MB8233.namprd12.prod.outlook.com> (raw)
In-Reply-To: <aPJxg1EpxkkcV83f@bricha3-mobl1.ger.corp.intel.com>
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[AMD Official Use Only - AMD Internal Distribution Only]
Hi Bruce,
________________________________
From: Bruce Richardson <bruce.richardson@intel.com>
Sent: Friday, October 17, 2025 10:10 PM
To: Tummala, Sivaprasad <Sivaprasad.Tummala@amd.com>
Cc: david.hunt@intel.com <david.hunt@intel.com>; honnappa.nagarahalli@arm.com <honnappa.nagarahalli@arm.com>; anatoly.burakov@intel.com <anatoly.burakov@intel.com>; jerinj@marvell.com <jerinj@marvell.com>; radu.nicolau@intel.com <radu.nicolau@intel.com>; gakhil@marvell.com <gakhil@marvell.com>; cristian.dumitrescu@intel.com <cristian.dumitrescu@intel.com>; Yigit, Ferruh <Ferruh.Yigit@amd.com>; konstantin.ananyev@huawei.com <konstantin.ananyev@huawei.com>; dev@dpdk.org <dev@dpdk.org>
Subject: Re: [PATCH] test/ring_perf: add optional cross L3 core selection
Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding.
On Fri, Oct 17, 2025 at 04:34:04PM +0000, Sivaprasad Tummala wrote:
>> Enhances test_ring_perf to optionally select two cores on
>> the same socket but on different L3 caches using hwloc.
>>
>> This allows performance characterization of ring library
>> on processors with split L3 cache architectures, providing
>> more realistic measurements of inter-core communication
>> and cache effects.
>>
>> The feature is conditional on hwloc being present, ensuring
>> builds succeed on systems without hwloc.
>>
>> Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>
>> ---
>> app/test/test_ring_perf.c | 75 +++++++++++++++++++++++++++++++++++++++
>> config/meson.build | 8 +++++
>> 2 files changed, 83 insertions(+)
>>
>> diff --git a/app/test/test_ring_perf.c b/app/test/test_ring_perf.c
<snip>
>> diff --git a/config/meson.build b/config/meson.build
>> index b8c1f127a2..75630254f2 100644
>> --- a/config/meson.build
>> +++ b/config/meson.build
>> @@ -313,6 +313,14 @@ else
>> add_project_arguments('-include', 'rte_config.h', language: 'c')
>> endif
>>
>> +hwloc_dep = dependency('hwloc', required : false)
>> +if hwloc_dep.found()
>> + add_project_arguments('-DHAVE_HWLOC=1', language : 'c')
>> + add_project_link_arguments('-lhwloc', language: 'c')
>> + dpdk_extra_ldflags += '-lhwloc'
>> + message('hwloc found — enabling L3 cache–aware topology support')
>> +endif
>> +
>
> Hi,
>
> I think this is the wrong place to put this. This will make the whole DPDK
> build depend on hwloc and add it to the pkg-config file.
>
> Instead, it's only the unit test binary that actually has the dependency,
> based on this patch, so just add the dep there, and add it to the cflags
> for that component only.
>
>/Bruce
ACK, I’ll restrict the hwloc dependency and related flag to the test application only in v2.
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prev parent reply other threads:[~2025-10-18 4:38 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-17 16:34 Sivaprasad Tummala
2025-10-17 16:40 ` Bruce Richardson
2025-10-18 4:38 ` Tummala, Sivaprasad [this message]
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