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* [PATCH] test/ring_perf: add optional cross L3 core selection
@ 2025-10-17 16:34 Sivaprasad Tummala
  2025-10-17 16:40 ` Bruce Richardson
  0 siblings, 1 reply; 3+ messages in thread
From: Sivaprasad Tummala @ 2025-10-17 16:34 UTC (permalink / raw)
  To: david.hunt, honnappa.nagarahalli, anatoly.burakov, jerinj,
	radu.nicolau, gakhil, cristian.dumitrescu, ferruh.yigit,
	konstantin.ananyev
  Cc: dev

Enhances test_ring_perf to optionally select two cores on
the same socket but on different L3 caches using hwloc.

This allows performance characterization of ring library
on processors with split L3 cache architectures, providing
more realistic measurements of inter-core communication
and cache effects.

The feature is conditional on hwloc being present, ensuring
builds succeed on systems without hwloc.

Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>
---
 app/test/test_ring_perf.c | 75 +++++++++++++++++++++++++++++++++++++++
 config/meson.build        |  8 +++++
 2 files changed, 83 insertions(+)

diff --git a/app/test/test_ring_perf.c b/app/test/test_ring_perf.c
index 9a2a481458..2003949649 100644
--- a/app/test/test_ring_perf.c
+++ b/app/test/test_ring_perf.c
@@ -15,6 +15,10 @@
 #include "test.h"
 #include "test_ring.h"
 
+#ifdef HAVE_HWLOC
+#include <hwloc.h>
+#endif /* HAVE_HWLOC */
+
 /*
  * Ring performance test cases, measures performance of various operations
  * using rdtsc for legacy and 16B size ring elements.
@@ -122,6 +126,69 @@ get_two_cores(struct lcore_pair *lcp)
 	return 1;
 }
 
+#ifdef HAVE_HWLOC
+
+#if HWLOC_API_VERSION < 0x20000
+#define hwloc_get_next_obj_cpuset_by_type_compat(t, s, ty, p) \
+	hwloc_get_next_obj_covering_cpuset_by_type(t, ty, p, s)
+#else
+#define hwloc_get_next_obj_cpuset_by_type_compat(t, s, ty, p) \
+	hwloc_get_next_obj_covering_cpuset_by_type(t, s, ty, p)
+#endif
+
+static int
+get_l3_cache_id(unsigned int cpu_id)
+{
+	hwloc_bitmap_t cpuset = hwloc_bitmap_alloc();
+	hwloc_topology_t topo;
+	hwloc_obj_t obj;
+	int l3_id = -1;
+
+	if (hwloc_topology_init(&topo) < 0 ||
+		hwloc_topology_load(topo) < 0) {
+		hwloc_bitmap_free(cpuset);
+		return -1;
+	}
+
+	hwloc_bitmap_only(cpuset, cpu_id);
+
+	obj = hwloc_get_next_obj_cpuset_by_type_compat(
+		topo, cpuset, HWLOC_OBJ_L3CACHE, NULL);
+
+	if (obj)
+		l3_id = (int)obj->logical_index;
+
+	hwloc_bitmap_free(cpuset);
+	hwloc_topology_destroy(topo);
+
+	return l3_id;
+}
+
+static int
+get_two_l3caches(struct lcore_pair *lcp)
+{
+	unsigned int id1, id2;
+	unsigned int c1, c2, s1, s2;
+	RTE_LCORE_FOREACH(id1) {
+		RTE_LCORE_FOREACH(id2) {
+			if (id1 == id2)
+				continue;
+
+			c1 = get_l3_cache_id(id1);
+			c2 = get_l3_cache_id(id2);
+			s1 = rte_lcore_to_socket_id(id1);
+			s2 = rte_lcore_to_socket_id(id2);
+			if ((c1 != c2) && (s1 == s2)) {
+				lcp->c1 = id1;
+				lcp->c2 = id2;
+				return 0;
+			}
+		}
+	}
+	return 1;
+}
+#endif /* HAVE_HWLOC */
+
 static int
 get_two_sockets(struct lcore_pair *lcp)
 {
@@ -483,6 +550,14 @@ test_ring_perf_esize_run_on_two_cores(
 		if (run_on_core_pair(&cores, param1, param2) < 0)
 			return -1;
 	}
+#ifdef HAVE_HWLOC
+	if (get_two_l3caches(&cores) == 0) {
+		printf("\n### Testing using two cores on same socket"
+			" with different L3 caches ###\n");
+		if (run_on_core_pair(&cores, param1, param2) < 0)
+			return -1;
+	}
+#endif /* HAVE_HWLOC */
 	if (get_two_sockets(&cores) == 0) {
 		printf("\n### Testing using two NUMA nodes ###\n");
 		if (run_on_core_pair(&cores, param1, param2) < 0)
diff --git a/config/meson.build b/config/meson.build
index b8c1f127a2..75630254f2 100644
--- a/config/meson.build
+++ b/config/meson.build
@@ -313,6 +313,14 @@ else
     add_project_arguments('-include', 'rte_config.h', language: 'c')
 endif
 
+hwloc_dep = dependency('hwloc', required : false)
+if hwloc_dep.found()
+  add_project_arguments('-DHAVE_HWLOC=1', language : 'c')
+  add_project_link_arguments('-lhwloc', language: 'c')
+  dpdk_extra_ldflags += '-lhwloc'
+  message('hwloc found — enabling L3 cache–aware topology support')
+endif
+
 # enable extra warnings and disable any unwanted warnings
 # -Wall is added by default at warning level 1, and -Wextra
 # at warning level 2 (DPDK default)
-- 
2.43.0


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH] test/ring_perf: add optional cross L3 core selection
  2025-10-17 16:34 [PATCH] test/ring_perf: add optional cross L3 core selection Sivaprasad Tummala
@ 2025-10-17 16:40 ` Bruce Richardson
  2025-10-18  4:38   ` Tummala, Sivaprasad
  0 siblings, 1 reply; 3+ messages in thread
From: Bruce Richardson @ 2025-10-17 16:40 UTC (permalink / raw)
  To: Sivaprasad Tummala
  Cc: david.hunt, honnappa.nagarahalli, anatoly.burakov, jerinj,
	radu.nicolau, gakhil, cristian.dumitrescu, ferruh.yigit,
	konstantin.ananyev, dev

On Fri, Oct 17, 2025 at 04:34:04PM +0000, Sivaprasad Tummala wrote:
> Enhances test_ring_perf to optionally select two cores on
> the same socket but on different L3 caches using hwloc.
> 
> This allows performance characterization of ring library
> on processors with split L3 cache architectures, providing
> more realistic measurements of inter-core communication
> and cache effects.
> 
> The feature is conditional on hwloc being present, ensuring
> builds succeed on systems without hwloc.
> 
> Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>
> ---
>  app/test/test_ring_perf.c | 75 +++++++++++++++++++++++++++++++++++++++
>  config/meson.build        |  8 +++++
>  2 files changed, 83 insertions(+)
> 
> diff --git a/app/test/test_ring_perf.c b/app/test/test_ring_perf.c

<snip>

> diff --git a/config/meson.build b/config/meson.build
> index b8c1f127a2..75630254f2 100644
> --- a/config/meson.build
> +++ b/config/meson.build
> @@ -313,6 +313,14 @@ else
>      add_project_arguments('-include', 'rte_config.h', language: 'c')
>  endif
>  
> +hwloc_dep = dependency('hwloc', required : false)
> +if hwloc_dep.found()
> +  add_project_arguments('-DHAVE_HWLOC=1', language : 'c')
> +  add_project_link_arguments('-lhwloc', language: 'c')
> +  dpdk_extra_ldflags += '-lhwloc'
> +  message('hwloc found — enabling L3 cache–aware topology support')
> +endif
> +

Hi,

I think this is the wrong place to put this. This will make the whole DPDK
build depend on hwloc and add it to the pkg-config file.

Instead, it's only the unit test binary that actually has the dependency,
based on this patch, so just add the dep there, and add it to the cflags
for that component only.

/Bruce

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH] test/ring_perf: add optional cross L3 core selection
  2025-10-17 16:40 ` Bruce Richardson
@ 2025-10-18  4:38   ` Tummala, Sivaprasad
  0 siblings, 0 replies; 3+ messages in thread
From: Tummala, Sivaprasad @ 2025-10-18  4:38 UTC (permalink / raw)
  To: Bruce Richardson
  Cc: david.hunt, honnappa.nagarahalli, anatoly.burakov, jerinj,
	radu.nicolau, gakhil, cristian.dumitrescu, Yigit, Ferruh,
	konstantin.ananyev, dev

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[AMD Official Use Only - AMD Internal Distribution Only]

Hi Bruce,

________________________________
From: Bruce Richardson <bruce.richardson@intel.com>
Sent: Friday, October 17, 2025 10:10 PM
To: Tummala, Sivaprasad <Sivaprasad.Tummala@amd.com>
Cc: david.hunt@intel.com <david.hunt@intel.com>; honnappa.nagarahalli@arm.com <honnappa.nagarahalli@arm.com>; anatoly.burakov@intel.com <anatoly.burakov@intel.com>; jerinj@marvell.com <jerinj@marvell.com>; radu.nicolau@intel.com <radu.nicolau@intel.com>; gakhil@marvell.com <gakhil@marvell.com>; cristian.dumitrescu@intel.com <cristian.dumitrescu@intel.com>; Yigit, Ferruh <Ferruh.Yigit@amd.com>; konstantin.ananyev@huawei.com <konstantin.ananyev@huawei.com>; dev@dpdk.org <dev@dpdk.org>
Subject: Re: [PATCH] test/ring_perf: add optional cross L3 core selection

Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding.


On Fri, Oct 17, 2025 at 04:34:04PM +0000, Sivaprasad Tummala wrote:
>> Enhances test_ring_perf to optionally select two cores on
>> the same socket but on different L3 caches using hwloc.
>>
>> This allows performance characterization of ring library
>> on processors with split L3 cache architectures, providing
>> more realistic measurements of inter-core communication
>> and cache effects.
>>
>> The feature is conditional on hwloc being present, ensuring
>> builds succeed on systems without hwloc.
>>
>> Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>
>> ---
>>  app/test/test_ring_perf.c | 75 +++++++++++++++++++++++++++++++++++++++
>>  config/meson.build        |  8 +++++
>>  2 files changed, 83 insertions(+)
>>
>> diff --git a/app/test/test_ring_perf.c b/app/test/test_ring_perf.c

<snip>

>> diff --git a/config/meson.build b/config/meson.build
>> index b8c1f127a2..75630254f2 100644
>> --- a/config/meson.build
>> +++ b/config/meson.build
>> @@ -313,6 +313,14 @@ else
>>      add_project_arguments('-include', 'rte_config.h', language: 'c')
>>  endif
>>
>> +hwloc_dep = dependency('hwloc', required : false)
>> +if hwloc_dep.found()
>> +  add_project_arguments('-DHAVE_HWLOC=1', language : 'c')
>> +  add_project_link_arguments('-lhwloc', language: 'c')
>> +  dpdk_extra_ldflags += '-lhwloc'
>> +  message('hwloc found — enabling L3 cache–aware topology support')
>> +endif
>> +
>
> Hi,
>
> I think this is the wrong place to put this. This will make the whole DPDK
> build depend on hwloc and add it to the pkg-config file.
>
> Instead, it's only the unit test binary that actually has the dependency,
> based on this patch, so just add the dep there, and add it to the cflags
> for that component only.
>
>/Bruce
ACK, I’ll restrict the hwloc dependency and related flag to the test application only in v2.

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^ permalink raw reply	[flat|nested] 3+ messages in thread

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2025-10-17 16:34 [PATCH] test/ring_perf: add optional cross L3 core selection Sivaprasad Tummala
2025-10-17 16:40 ` Bruce Richardson
2025-10-18  4:38   ` Tummala, Sivaprasad

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