From: "Tummala, Sivaprasad" <Sivaprasad.Tummala@amd.com>
To: Bruce Richardson <bruce.richardson@intel.com>
Cc: "honnappa.nagarahalli@arm.com" <honnappa.nagarahalli@arm.com>,
"anatoly.burakov@intel.com" <anatoly.burakov@intel.com>,
"jerinj@marvell.com" <jerinj@marvell.com>,
"radu.nicolau@intel.com" <radu.nicolau@intel.com>,
"gakhil@marvell.com" <gakhil@marvell.com>,
"cristian.dumitrescu@intel.com" <cristian.dumitrescu@intel.com>,
"Yigit, Ferruh" <Ferruh.Yigit@amd.com>,
"konstantin.ananyev@huawei.com" <konstantin.ananyev@huawei.com>,
"dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [PATCH v2] test/ring_perf: add optional cross L3 core selection
Date: Mon, 20 Oct 2025 23:26:57 +0000 [thread overview]
Message-ID: <CH3PR12MB8233E5E483D25DC3F463F89386F5A@CH3PR12MB8233.namprd12.prod.outlook.com> (raw)
In-Reply-To: <aPX5bkbE-V43O_Tq@bricha3-mobl1.ger.corp.intel.com>
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[AMD Official Use Only - AMD Internal Distribution Only]
Hi Bruce,
________________________________
From: Bruce Richardson <bruce.richardson@intel.com>
Sent: Monday, October 20, 2025 2:27 PM
To: Tummala, Sivaprasad <Sivaprasad.Tummala@amd.com>
Cc: honnappa.nagarahalli@arm.com <honnappa.nagarahalli@arm.com>; anatoly.burakov@intel.com <anatoly.burakov@intel.com>; jerinj@marvell.com <jerinj@marvell.com>; radu.nicolau@intel.com <radu.nicolau@intel.com>; gakhil@marvell.com <gakhil@marvell.com>; cristian.dumitrescu@intel.com <cristian.dumitrescu@intel.com>; Yigit, Ferruh <Ferruh.Yigit@amd.com>; konstantin.ananyev@huawei.com <konstantin.ananyev@huawei.com>; dev@dpdk.org <dev@dpdk.org>
Subject: Re: [PATCH v2] test/ring_perf: add optional cross L3 core selection
Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding.
On Sat, Oct 18, 2025 at 06:48:27AM +0000, Sivaprasad Tummala wrote:
>> Enhances test_ring_perf to optionally select two cores on
>> the same socket but on different L3 caches using hwloc.
>>
>> This allows performance characterization of ring library
>> on processors with split L3 cache architectures, providing
>> more realistic measurements of inter-core communication
>> and cache effects.
>>
>> The feature is conditional on hwloc being present, ensuring
>> builds succeed on systems without hwloc.
>>
>> Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>
>>
>> v2:
>> * Localized hwloc dependency to test app only.
>> * Optimized get_two_l3caches() by moving socket and L3 cache ID
>> retrieval to the outer loop.
>> ---
>> app/meson.build | 8 ++++-
>> app/test/test_ring_perf.c | 76 +++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 83 insertions(+), 1 deletion(-)
>>
>> diff --git a/app/meson.build b/app/meson.build
>> index 1798db3ae4..5443043f0c 100644
>> --- a/app/meson.build
>> +++ b/app/meson.build
>> @@ -46,6 +46,12 @@ if get_option('default_library') == 'static' and not is_windows
>> default_ldflags += ['-Wl,--export-dynamic']
>> endif
>>
>> +hwloc_dep = dependency('hwloc', required : false)
>> +if hwloc_dep.found()
>> + default_cflags += ['-DHAVE_HWLOC=1']
>> + message('hwloc found — enabling L3 cache–aware topology support')
>> +endif
>> +
>> foreach app:apps
>> name = app
>> build = true
>> @@ -60,7 +66,7 @@ foreach app:apps
>>
>> # use "deps" for internal DPDK dependencies, and "ext_deps" for
>> # external package/library requirements
>> - ext_deps = []
>> + ext_deps = [hwloc_dep]
>> deps = []
>>
>> if not enable_apps.contains(app)
>
>I still think we can limit this more. No need, for example, for test-pmd or
>test-cmdline, for that matter, to depend on hwloc. Therefore, I'd suggest
>moving the dependency code to app/test/meson.build and adding it there.
>
>/Bruce
ACK! Will fix this in v3
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prev parent reply other threads:[~2025-10-20 23:27 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <https://patches.dpdk.org/project/dpdk/patch/20251017163407.845502-1-sivaprasad.tummala@amd.com>
2025-10-18 6:48 ` Sivaprasad Tummala
2025-10-20 8:57 ` Bruce Richardson
2025-10-20 23:26 ` Tummala, Sivaprasad [this message]
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