* [PATCH v2] test/ring_perf: add optional cross L3 core selection [not found] <https://patches.dpdk.org/project/dpdk/patch/20251017163407.845502-1-sivaprasad.tummala@amd.com> @ 2025-10-18 6:48 ` Sivaprasad Tummala 2025-10-20 8:57 ` Bruce Richardson 0 siblings, 1 reply; 3+ messages in thread From: Sivaprasad Tummala @ 2025-10-18 6:48 UTC (permalink / raw) To: bruce.richardson, honnappa.nagarahalli, anatoly.burakov, jerinj, radu.nicolau, gakhil, cristian.dumitrescu, ferruh.yigit, konstantin.ananyev Cc: dev Enhances test_ring_perf to optionally select two cores on the same socket but on different L3 caches using hwloc. This allows performance characterization of ring library on processors with split L3 cache architectures, providing more realistic measurements of inter-core communication and cache effects. The feature is conditional on hwloc being present, ensuring builds succeed on systems without hwloc. Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com> v2: * Localized hwloc dependency to test app only. * Optimized get_two_l3caches() by moving socket and L3 cache ID retrieval to the outer loop. --- app/meson.build | 8 ++++- app/test/test_ring_perf.c | 76 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+), 1 deletion(-) diff --git a/app/meson.build b/app/meson.build index 1798db3ae4..5443043f0c 100644 --- a/app/meson.build +++ b/app/meson.build @@ -46,6 +46,12 @@ if get_option('default_library') == 'static' and not is_windows default_ldflags += ['-Wl,--export-dynamic'] endif +hwloc_dep = dependency('hwloc', required : false) +if hwloc_dep.found() + default_cflags += ['-DHAVE_HWLOC=1'] + message('hwloc found — enabling L3 cache–aware topology support') +endif + foreach app:apps name = app build = true @@ -60,7 +66,7 @@ foreach app:apps # use "deps" for internal DPDK dependencies, and "ext_deps" for # external package/library requirements - ext_deps = [] + ext_deps = [hwloc_dep] deps = [] if not enable_apps.contains(app) diff --git a/app/test/test_ring_perf.c b/app/test/test_ring_perf.c index 9a2a481458..51585d647b 100644 --- a/app/test/test_ring_perf.c +++ b/app/test/test_ring_perf.c @@ -15,6 +15,10 @@ #include "test.h" #include "test_ring.h" +#ifdef HAVE_HWLOC +#include <hwloc.h> +#endif /* HAVE_HWLOC */ + /* * Ring performance test cases, measures performance of various operations * using rdtsc for legacy and 16B size ring elements. @@ -122,6 +126,70 @@ get_two_cores(struct lcore_pair *lcp) return 1; } +#ifdef HAVE_HWLOC + +#if HWLOC_API_VERSION < 0x20000 +#define hwloc_get_next_obj_cpuset_by_type_compat(t, s, ty, p) \ + hwloc_get_next_obj_covering_cpuset_by_type(t, ty, p, s) +#else +#define hwloc_get_next_obj_cpuset_by_type_compat(t, s, ty, p) \ + hwloc_get_next_obj_covering_cpuset_by_type(t, s, ty, p) +#endif + +static int +get_l3_cache_id(unsigned int cpu_id) +{ + hwloc_bitmap_t cpuset = hwloc_bitmap_alloc(); + hwloc_topology_t topo; + hwloc_obj_t obj; + int l3_id = -1; + + if (hwloc_topology_init(&topo) < 0 || + hwloc_topology_load(topo) < 0) { + hwloc_bitmap_free(cpuset); + return -1; + } + + hwloc_bitmap_only(cpuset, cpu_id); + + obj = hwloc_get_next_obj_cpuset_by_type_compat( + topo, cpuset, HWLOC_OBJ_L3CACHE, NULL); + + if (obj) + l3_id = (int)obj->logical_index; + + hwloc_bitmap_free(cpuset); + hwloc_topology_destroy(topo); + + return l3_id; +} + +static int +get_two_l3caches(struct lcore_pair *lcp) +{ + unsigned int id1, id2; + unsigned int c1, c2, s1, s2; + RTE_LCORE_FOREACH(id1) { + c1 = get_l3_cache_id(id1); + s1 = rte_lcore_to_socket_id(id1); + + RTE_LCORE_FOREACH(id2) { + if (id1 == id2) + continue; + + c2 = get_l3_cache_id(id2); + s2 = rte_lcore_to_socket_id(id2); + if ((c1 != c2) && (s1 == s2)) { + lcp->c1 = id1; + lcp->c2 = id2; + return 0; + } + } + } + return 1; +} +#endif /* HAVE_HWLOC */ + static int get_two_sockets(struct lcore_pair *lcp) { @@ -483,6 +551,14 @@ test_ring_perf_esize_run_on_two_cores( if (run_on_core_pair(&cores, param1, param2) < 0) return -1; } +#ifdef HAVE_HWLOC + if (get_two_l3caches(&cores) == 0) { + printf("\n### Testing using two cores on same socket" + " with different L3 caches ###\n"); + if (run_on_core_pair(&cores, param1, param2) < 0) + return -1; + } +#endif /* HAVE_HWLOC */ if (get_two_sockets(&cores) == 0) { printf("\n### Testing using two NUMA nodes ###\n"); if (run_on_core_pair(&cores, param1, param2) < 0) -- 2.43.0 ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] test/ring_perf: add optional cross L3 core selection 2025-10-18 6:48 ` [PATCH v2] test/ring_perf: add optional cross L3 core selection Sivaprasad Tummala @ 2025-10-20 8:57 ` Bruce Richardson 2025-10-20 23:26 ` Tummala, Sivaprasad 0 siblings, 1 reply; 3+ messages in thread From: Bruce Richardson @ 2025-10-20 8:57 UTC (permalink / raw) To: Sivaprasad Tummala Cc: honnappa.nagarahalli, anatoly.burakov, jerinj, radu.nicolau, gakhil, cristian.dumitrescu, ferruh.yigit, konstantin.ananyev, dev On Sat, Oct 18, 2025 at 06:48:27AM +0000, Sivaprasad Tummala wrote: > Enhances test_ring_perf to optionally select two cores on > the same socket but on different L3 caches using hwloc. > > This allows performance characterization of ring library > on processors with split L3 cache architectures, providing > more realistic measurements of inter-core communication > and cache effects. > > The feature is conditional on hwloc being present, ensuring > builds succeed on systems without hwloc. > > Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com> > > v2: > * Localized hwloc dependency to test app only. > * Optimized get_two_l3caches() by moving socket and L3 cache ID > retrieval to the outer loop. > --- > app/meson.build | 8 ++++- > app/test/test_ring_perf.c | 76 +++++++++++++++++++++++++++++++++++++++ > 2 files changed, 83 insertions(+), 1 deletion(-) > > diff --git a/app/meson.build b/app/meson.build > index 1798db3ae4..5443043f0c 100644 > --- a/app/meson.build > +++ b/app/meson.build > @@ -46,6 +46,12 @@ if get_option('default_library') == 'static' and not is_windows > default_ldflags += ['-Wl,--export-dynamic'] > endif > > +hwloc_dep = dependency('hwloc', required : false) > +if hwloc_dep.found() > + default_cflags += ['-DHAVE_HWLOC=1'] > + message('hwloc found — enabling L3 cache–aware topology support') > +endif > + > foreach app:apps > name = app > build = true > @@ -60,7 +66,7 @@ foreach app:apps > > # use "deps" for internal DPDK dependencies, and "ext_deps" for > # external package/library requirements > - ext_deps = [] > + ext_deps = [hwloc_dep] > deps = [] > > if not enable_apps.contains(app) I still think we can limit this more. No need, for example, for test-pmd or test-cmdline, for that matter, to depend on hwloc. Therefore, I'd suggest moving the dependency code to app/test/meson.build and adding it there. /Bruce ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] test/ring_perf: add optional cross L3 core selection 2025-10-20 8:57 ` Bruce Richardson @ 2025-10-20 23:26 ` Tummala, Sivaprasad 0 siblings, 0 replies; 3+ messages in thread From: Tummala, Sivaprasad @ 2025-10-20 23:26 UTC (permalink / raw) To: Bruce Richardson Cc: honnappa.nagarahalli, anatoly.burakov, jerinj, radu.nicolau, gakhil, cristian.dumitrescu, Yigit, Ferruh, konstantin.ananyev, dev [-- Attachment #1: Type: text/plain, Size: 2981 bytes --] [AMD Official Use Only - AMD Internal Distribution Only] Hi Bruce, ________________________________ From: Bruce Richardson <bruce.richardson@intel.com> Sent: Monday, October 20, 2025 2:27 PM To: Tummala, Sivaprasad <Sivaprasad.Tummala@amd.com> Cc: honnappa.nagarahalli@arm.com <honnappa.nagarahalli@arm.com>; anatoly.burakov@intel.com <anatoly.burakov@intel.com>; jerinj@marvell.com <jerinj@marvell.com>; radu.nicolau@intel.com <radu.nicolau@intel.com>; gakhil@marvell.com <gakhil@marvell.com>; cristian.dumitrescu@intel.com <cristian.dumitrescu@intel.com>; Yigit, Ferruh <Ferruh.Yigit@amd.com>; konstantin.ananyev@huawei.com <konstantin.ananyev@huawei.com>; dev@dpdk.org <dev@dpdk.org> Subject: Re: [PATCH v2] test/ring_perf: add optional cross L3 core selection Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding. On Sat, Oct 18, 2025 at 06:48:27AM +0000, Sivaprasad Tummala wrote: >> Enhances test_ring_perf to optionally select two cores on >> the same socket but on different L3 caches using hwloc. >> >> This allows performance characterization of ring library >> on processors with split L3 cache architectures, providing >> more realistic measurements of inter-core communication >> and cache effects. >> >> The feature is conditional on hwloc being present, ensuring >> builds succeed on systems without hwloc. >> >> Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com> >> >> v2: >> * Localized hwloc dependency to test app only. >> * Optimized get_two_l3caches() by moving socket and L3 cache ID >> retrieval to the outer loop. >> --- >> app/meson.build | 8 ++++- >> app/test/test_ring_perf.c | 76 +++++++++++++++++++++++++++++++++++++++ >> 2 files changed, 83 insertions(+), 1 deletion(-) >> >> diff --git a/app/meson.build b/app/meson.build >> index 1798db3ae4..5443043f0c 100644 >> --- a/app/meson.build >> +++ b/app/meson.build >> @@ -46,6 +46,12 @@ if get_option('default_library') == 'static' and not is_windows >> default_ldflags += ['-Wl,--export-dynamic'] >> endif >> >> +hwloc_dep = dependency('hwloc', required : false) >> +if hwloc_dep.found() >> + default_cflags += ['-DHAVE_HWLOC=1'] >> + message('hwloc found — enabling L3 cache–aware topology support') >> +endif >> + >> foreach app:apps >> name = app >> build = true >> @@ -60,7 +66,7 @@ foreach app:apps >> >> # use "deps" for internal DPDK dependencies, and "ext_deps" for >> # external package/library requirements >> - ext_deps = [] >> + ext_deps = [hwloc_dep] >> deps = [] >> >> if not enable_apps.contains(app) > >I still think we can limit this more. No need, for example, for test-pmd or >test-cmdline, for that matter, to depend on hwloc. Therefore, I'd suggest >moving the dependency code to app/test/meson.build and adding it there. > >/Bruce ACK! Will fix this in v3 [-- Attachment #2: Type: text/html, Size: 5426 bytes --] ^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-10-18 6:48 ` [PATCH v2] test/ring_perf: add optional cross L3 core selection Sivaprasad Tummala
2025-10-20 8:57 ` Bruce Richardson
2025-10-20 23:26 ` Tummala, Sivaprasad
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