From: Dariusz Sosnowski <dsosnowski@nvidia.com>
To: Bing Zhao <bingz@nvidia.com>,
"Jiawei(Jonny) Wang" <jiaweiw@nvidia.com>,
Suanming Mou <suanmingm@nvidia.com>,
Xueming Li <xuemingl@nvidia.com>,
Slava Ovsiienko <viacheslavo@nvidia.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>, Raslan Darawsheh <rasland@nvidia.com>
Subject: RE: [PATCH] net/mlx5: support no host PF configuration
Date: Mon, 28 Oct 2024 09:35:00 +0000 [thread overview]
Message-ID: <CH3PR12MB8460672E690CA107BF5ADD1CA44A2@CH3PR12MB8460.namprd12.prod.outlook.com> (raw)
In-Reply-To: <PH7PR12MB69053638E73E2E498ABD9099D06B2@PH7PR12MB6905.namprd12.prod.outlook.com>
> -----Original Message-----
> From: Bing Zhao <bingz@nvidia.com>
> Sent: Friday, September 27, 2024 09:12
> To: Jiawei(Jonny) Wang <jiaweiw@nvidia.com>; Suanming Mou
> <suanmingm@nvidia.com>; Xueming Li <xuemingl@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>
> Cc: dev@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>
> Subject: RE: [PATCH] net/mlx5: support no host PF configuration
>
> External email: Use caution opening links or attachments
>
>
> Hi,
>
> > -----Original Message-----
> > From: Jiawei Wang <jiaweiw@nvidia.com>
> > Sent: Wednesday, October 11, 2023 2:42 PM
> > To: Suanming Mou <suanmingm@nvidia.com>; Xueming(Steven) Li
> > <xuemingl@nvidia.com>; Slava Ovsiienko <viacheslavo@nvidia.com>
> > Cc: dev@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>
> > Subject: [PATCH] net/mlx5: support no host PF configuration
> >
> > External email: Use caution opening links or attachments
> >
> >
> > From: Xueming Li <xuemingl@nvidia.com>
> >
> > In BlueField, a new firmware configuration option NUM_OF_PF=0 disables
> > PF on the x86 host side, no HPF on the ARM side, and the only RDMA
> > port on the ARM side is the bonding device(PF0). A device probe with
> > devargs of representor=pf[0-1]vf[...] will probe PF0 and PF1 one by
> > one, and it's possible that PF1 device scan results in no switch ports.
> >
> > This patch supports the new configuration by allowing a PF scan with
> > empty switch ports.
> >
> > Signed-off-by: Xueming Li <xuemingl@nvidia.com>
> > Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
> > ---
> > drivers/net/mlx5/linux/mlx5_os.c | 7 -------
> > 1 file changed, 7 deletions(-)
> >
> > diff --git a/drivers/net/mlx5/linux/mlx5_os.c
> > b/drivers/net/mlx5/linux/mlx5_os.c
> > index d5ef695e6d..75f53ade8e 100644
> > --- a/drivers/net/mlx5/linux/mlx5_os.c
> > +++ b/drivers/net/mlx5/linux/mlx5_os.c
> > @@ -2195,13 +2195,6 @@ mlx5_os_pci_probe_pf(struct
> mlx5_common_device
> > *cdev,
> > list[ns].info.master))
> > ns++;
> > }
> > - if (!ns) {
> > - DRV_LOG(ERR,
> > - "Unable to recognize master/representors
> > on the IB device with multiple ports.");
> > - rte_errno = ENOENT;
> > - ret = -rte_errno;
> > - goto exit;
> > - }
> > } else {
> > /*
> > * The existence of several matching entries (nd > 1)
> > means
> > --
>
> Acked-by: Bing Zhao <bingz@nvidia.com>
>
> Thanks
>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Best regards,
Dariusz Sosnowski
next prev parent reply other threads:[~2024-10-28 9:35 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-11 6:41 Jiawei Wang
2024-09-27 7:11 ` Bing Zhao
2024-10-28 9:35 ` Dariusz Sosnowski [this message]
2024-10-07 18:09 ` Stephen Hemminger
2024-10-28 13:12 ` Raslan Darawsheh
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