From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5EEE543C3B; Thu, 29 Feb 2024 17:04:23 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DB13342E2B; Thu, 29 Feb 2024 17:04:16 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B55C442DBE for ; Thu, 29 Feb 2024 17:04:15 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41T8pFKm002573; Thu, 29 Feb 2024 08:04:15 -0800 Received: from nam04-bn8-obe.outbound.protection.outlook.com (mail-bn8nam04lp2040.outbound.protection.outlook.com [104.47.74.40]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3wjfay3j18-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Feb 2024 08:04:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=a8Ryu0O7yV5HfsHf65cLGadJoix7BVgZ2mbqbF0a0j1DMi3EEvyDTZ4b8YmJUEkdrYof844z1EKBNzfdLcLCo0rXH4LthXUaGFton+gZ42U162/dJj8e218V+LaPSK+kUDaQd/FxK/r/xnaOrEsXcRtHdXUwlFpwe2qu5Xe4tlSEwPDUZf407+wba8sOiiGRaH979vxE+V4aP2IuodSYOopKuTARrFOLj50nJa8PfVI/57vpW/8YvSuw7fq2BhH6F3aq4tpam4Lj9wz42NikNwAMdwXSM33tleRWOk5Y9GOSnhTHCaEsaOtjhiQznp/JCz1KY2mdm0jKNxAy+s/OyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=wJ+PX8RMsasb8pChNLdORMb/EACkGgk06mUul+z2mow=; b=Gu/2nIiAUbuM07x3tMPpqty054ZLXQqmWELzjW6QR9G7hxSglLpW+aZdvwRHMxOVHQvk8bBSbOGJTydPtMQG29/7op3s9Ke2XxWQtHosYcXpL5L+a7ZfvQzPbK/CtOSi2uk5zEbbBoPRX4/y2tVN8zKVd7FUhbbliorQUivvwdBg2aPawRPQABxdD6wbvcvQ5dzeJ3HT0JKN78NZHBtP6ijn0bFro3G+wL2zgojgWbOt61/I5Fhv7yMVQU/e1jBnDxUvrRmz/qJP2yHYu7T5cT64K6Uje+KBMQMCQIdOETSPBL078yw7oBdrldU8i+WzRzGMeTGCq1eXWhq8GvgnsA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=marvell.com; dmarc=pass action=none header.from=marvell.com; dkim=pass header.d=marvell.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.onmicrosoft.com; s=selector1-marvell-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wJ+PX8RMsasb8pChNLdORMb/EACkGgk06mUul+z2mow=; b=brt+AaX9P0yPdfgtlfAB28WS1HxPg8HHzORaXBjA+k6YSMomBZEXB0d3NfUh70PvpFCuAsr6cDY5dFlFdSfG+vY4dAYKzM8CNnox1ktU0UCX6x5erbJNESF+JxFHqfjhHLsd++Ld4mN47MnoaP7z3wFlq0JsX/fK5DcKJokPIUo= Received: from CO6PR18MB4484.namprd18.prod.outlook.com (2603:10b6:5:359::9) by CO1PR18MB4777.namprd18.prod.outlook.com (2603:10b6:303:ec::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7316.41; Thu, 29 Feb 2024 16:04:08 +0000 Received: from CO6PR18MB4484.namprd18.prod.outlook.com ([fe80::9345:cddf:24ca:5be9]) by CO6PR18MB4484.namprd18.prod.outlook.com ([fe80::9345:cddf:24ca:5be9%4]) with mapi id 15.20.7316.039; Thu, 29 Feb 2024 16:04:08 +0000 From: Akhil Goyal To: Nishikant Nayak , "dev@dpdk.org" CC: "ciara.power@intel.com" , "kai.ji@intel.com" , "arkadiuszx.kusztal@intel.com" , "rakesh.s.joshi@intel.com" Subject: RE: [EXT] [PATCH v6 3/4] crypto/qat: update headers for GEN LCE support Thread-Topic: [EXT] [PATCH v6 3/4] crypto/qat: update headers for GEN LCE support Thread-Index: AQHaak6fze59Un6aWE2lU+6q1Lzqo7Ehey8A Date: Thu, 29 Feb 2024 16:04:08 +0000 Message-ID: References: <20231220132616.318983-1-nishikanta.nayak@intel.com> <20240228140036.1996629-1-nishikanta.nayak@intel.com> <20240228140036.1996629-4-nishikanta.nayak@intel.com> In-Reply-To: <20240228140036.1996629-4-nishikanta.nayak@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: CO6PR18MB4484:EE_|CO1PR18MB4777:EE_ x-ms-office365-filtering-correlation-id: 9f007882-0993-4fbd-87ec-08dc39400fb7 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: dMQ+eMGrx/d8WMWi+xCWhyWpOyG2vgLESMLIsn/ccr51hBi6irwzaHqbCHvwWaglSb+adEzKZwSCFYHqo+Lb+5gfyyFOf9xPQJLty/82IZhRjAQsdL9bdmclXEQdVTWYYe7jlG/B4iFljnU3Vh9JCJ1kfeWeaS9PSFog6q9np5jcOCNF20puke63GX2ZdAO9cwCTrR9G/TaQI/Qx4VJobZgIpxixJ3RpyyCo/kyDLOAFwg6iHsHxsXTUxppSxmySibKDVd50IFuarMw+uaIzvOVTj1GlXl2m1MlMmVw+hkt/0statIBJV29QQOw5cHopJbq/QKGrpFUM+DxhDUp5z/Uhi/6q3/3XCgI3ffwjhJs6zZQaINpIncjax7vxevnf7RvcKEsVdhuAZ+1h44Rk0k05Hz7ZGIdIGmsmpDcSr4aCqfibyMA5B8PLpa7UKqGK5vVDiaAjO8o0naXTn5n5bjPhVXYZsYWtuL2XSun6ZQvwhFTsVTrXkE8SKimAxpWEse0A3mKTgrqDI8t7R3DDc0f/H1zCHbLAv/IFt1Hls1zqzW02fMQ9iL2hIg8qex/6o/wehLUc5l8oYOSB42OeJlWhr+9lWSKcXSM1wTBWt96FJPc5m5egouM4Tff1dUZY9zRLGl5O9NHbM/RbMH3h26Y9ofKMwaz4ymaWKXwe5T9c+J/CpdA7/NlAq+3YWmCiUHlAvFo27xLR2V5gyo0+qPT7sfRTuOAlBjA/LZcpUko= x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:CO6PR18MB4484.namprd18.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(38070700009); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?QKeCg8MVhU18x547eJKO6xnRYA3/2UxM8WIhzil0raMGuZZy0llW612a4pLm?= =?us-ascii?Q?yJ2YTymDVBdYOnPKR4EF9pvmsaq+64Da6JcxidW/bKZsi+X8rirwMlJK+j4y?= =?us-ascii?Q?GlJ0p5RALe6B4gfiMLTBt84LOCQuDkA31F3hYlLpCp9hKqr1sXYj0alGxg9b?= =?us-ascii?Q?O1yd8apeATbcmMWVZZQUVU1kp1jyQJHfttQWVVzbpWW+hUbwPokzU496AzJk?= =?us-ascii?Q?nXL4AmV3wWuP/FlFdGRNECaZA3+j+Yf3qcLdSho8jxyvjLSXuohs+LyBv+n1?= =?us-ascii?Q?hQGJYK2GWBoh1zOmSVVNqwl+ioejj3vMFCi3+RLsz3amxqOJ+6VRlvlDmlyk?= =?us-ascii?Q?aJPEdyirpyUOfpWV+qGTV8OsE8we5Xc5VbT8ZPM7I3jL2YGRGbHlfvifEXqO?= =?us-ascii?Q?GKjgSYda1zR4y8gNhTP7iInxUXJI2pnVvXTQuG6BQi6CCnUh1y9DyWPIA5Ir?= =?us-ascii?Q?1I4h2niz6Crp2VKzwlSBLBX67Ezab4J1udRMbtVuja9QFXvlQIwvlU1gBpbJ?= =?us-ascii?Q?s5yT+WQLFeIP+tMMcnHsxpTlLx0BWj23x6zEu7NII1G/QaRP/RVMGOdPteKH?= =?us-ascii?Q?pB0uOoEso6ecRysGrM3r62RECVwNk+iXy+IaBHd8s4fkp0GZZrUXDXV+9Y1n?= =?us-ascii?Q?tHDbIHvPMtNdzj+Xml5gacFWfE25ZgQLVoLvM/C5v+P6+heqSM/0PaeUYxn6?= =?us-ascii?Q?clPMcsguIrmYIkbHRNshRVlOeufoeisCe6bsICKZcny/MnZl+HyMf2PyHFaD?= =?us-ascii?Q?HkVPLldYQpWPijINCm0tRadMNodU1DrBnmKsJyu/1AO83IOrXPlNXC3Mqm9Q?= =?us-ascii?Q?GGbv+2lCgu9MyyNKsRbf29IEkJlvCvCX50AdBqzPMU+eTmV1Al/zyO7Tu8GF?= =?us-ascii?Q?muGmnUBnw+nzkKJ3eMDlyfuUIT8RN7ndY+tvJByRHrKrsZZfvGkUEYLq15CK?= =?us-ascii?Q?SHONz/IvCn0wmLjtXdcQDoWi3ZTKKEno30aaGFF0dyWgZgs+w9o+HS2DoMXf?= =?us-ascii?Q?1G6CgIt3yC385WPnpI5VsZQ1fLibTN5XDseIS51ExiNBTouHcxK+g1BWYLu8?= =?us-ascii?Q?PTW8ook3iweM3570RNf8JYRdxpCbIT5jUAG2+JPkJYVJXFs/l2eZWikTRkRs?= =?us-ascii?Q?/nOdq4d8AjlVH/mqn7ajZVGYgQNte8DzcLZYydMX/sLKjbrugn8uaBTaDcyV?= =?us-ascii?Q?TgV1DOShadQaYIER4WWcdXOaQ1c3RFFeQ0Kt2SD2STlQMxlIDlNkbQ2/fWKb?= =?us-ascii?Q?bVPQ7TCdQrBfYEEiUmDowIRhIgFpA7tNNRBwUfp2oKU3eM9/ZtVNk7TeBh2N?= =?us-ascii?Q?ktLUFR7UfoEvMXOwoBJstNfbmtpFUELD/8Q7wvKJL8eGNuGLo+EIO085kDu4?= =?us-ascii?Q?DHM9fm8GJgQtKHXoLF1MS2co6FJPgPZJ/ZKdFBAnvwfLimZMDL1ypkeIq16S?= =?us-ascii?Q?+P90yEUQ9Ij3J+LCH/755EQm9fZnS2YSjkCX6ikTtyF5FDOeL/YvCs8IpRZg?= =?us-ascii?Q?QSvorpN5YNVpc3xtTX2gP8yHv5/0HHWfhsMBM2/KR1qZj0uhf+kGRRg0JrnY?= =?us-ascii?Q?yp8NYxOjEoSDivbF6bV29GgiIm3EkVbOSF/cRRp4?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO6PR18MB4484.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9f007882-0993-4fbd-87ec-08dc39400fb7 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Feb 2024 16:04:08.3667 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: EtAxRimZG6ackdBpRm3F+x1pnadnpf/kZNddKJjLkKzCXpUHQOBH1y5ZJMFGn3hjwvlz70FA/m1lHAub4zaUZw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR18MB4777 X-Proofpoint-ORIG-GUID: M9Ld54NySk3lEAcGli_-4cz-ZOTFh7oA X-Proofpoint-GUID: M9Ld54NySk3lEAcGli_-4cz-ZOTFh7oA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-29_02,2024-02-29_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > This patch handles the changes required for updating the common > header fields specific to GEN LCE, Also added/updated of the response > processing APIs based on GEN LCE requirement. >=20 > Signed-off-by: Nishikant Nayak > Acked-by: Ciara Power > --- > v2: > - Renamed device from GEN 5 to GEN LCE. > - Removed unused code. > - Updated macro names. > - Added GEN LCE specific API for deque burst. > - Fixed code formatting. > --- > --- > drivers/crypto/qat/qat_sym.c | 16 ++++++- > drivers/crypto/qat/qat_sym.h | 60 ++++++++++++++++++++++++++- > drivers/crypto/qat/qat_sym_session.c | 62 +++++++++++++++++++++++++++- > drivers/crypto/qat/qat_sym_session.h | 10 ++++- > 4 files changed, 140 insertions(+), 8 deletions(-) >=20 > diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c > index 6e03bde841..439a3fc00b 100644 > --- a/drivers/crypto/qat/qat_sym.c > +++ b/drivers/crypto/qat/qat_sym.c > @@ -180,7 +180,15 @@ qat_sym_dequeue_burst(void *qp, struct rte_crypto_op > **ops, > uint16_t nb_ops) > { > return qat_dequeue_op_burst(qp, (void **)ops, > - qat_sym_process_response, nb_ops); > + qat_sym_process_response, nb_ops); Unnecessary change. Please remove unnecessary changes which should not be p= art of this patch. The maximum length of characters in a line is 100 now. You can format the c= ode as per that. Since QAT has long macros etc. it would be better to leverage the 100 chara= cter per line. The code would look more readable. This is a general comment on the complete patchset. > +} > + > +uint16_t > +qat_sym_dequeue_burst_gen_lce(void *qp, struct rte_crypto_op **ops, > + uint16_t nb_ops) > +{ > + return qat_dequeue_op_burst(qp, (void **)ops, > + qat_sym_process_response_gen_lce, nb_ops); > } >=20 > int > @@ -200,6 +208,7 @@ qat_sym_dev_create(struct qat_pci_device > *qat_pci_dev, > char capa_memz_name[RTE_CRYPTODEV_NAME_MAX_LEN]; > struct rte_cryptodev *cryptodev; > struct qat_cryptodev_private *internals; > + enum qat_device_gen qat_dev_gen =3D qat_pci_dev->qat_dev_gen; > const struct qat_crypto_gen_dev_ops *gen_dev_ops =3D > &qat_sym_gen_dev_ops[qat_pci_dev->qat_dev_gen]; >=20 > @@ -249,7 +258,10 @@ qat_sym_dev_create(struct qat_pci_device > *qat_pci_dev, > cryptodev->dev_ops =3D gen_dev_ops->cryptodev_ops; >=20 > cryptodev->enqueue_burst =3D qat_sym_enqueue_burst; > - cryptodev->dequeue_burst =3D qat_sym_dequeue_burst; > + if (qat_dev_gen =3D=3D QAT_GEN_LCE) > + cryptodev->dequeue_burst =3D qat_sym_dequeue_burst_gen_lce; > + else > + cryptodev->dequeue_burst =3D qat_sym_dequeue_burst; >=20 > cryptodev->feature_flags =3D gen_dev_ops- > >get_feature_flags(qat_pci_dev); >=20 > diff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h > index f2f197d050..3461113c13 100644 > --- a/drivers/crypto/qat/qat_sym.h > +++ b/drivers/crypto/qat/qat_sym.h > @@ -90,7 +90,7 @@ > /* > * Maximum number of SGL entries > */ > -#define QAT_SYM_SGL_MAX_NUMBER 16 > +#define QAT_SYM_SGL_MAX_NUMBER 16 Again unnecessary change. >=20 > /* Maximum data length for single pass GMAC: 2^14-1 */ > #define QAT_AES_GMAC_SPC_MAX_SIZE 16383 > @@ -142,6 +142,10 @@ uint16_t > qat_sym_dequeue_burst(void *qp, struct rte_crypto_op **ops, > uint16_t nb_ops); >=20 > +uint16_t > +qat_sym_dequeue_burst_gen_lce(void *qp, struct rte_crypto_op **ops, > + uint16_t nb_ops); > + > #ifdef RTE_QAT_OPENSSL > /** Encrypt a single partial block > * Depends on openssl libcrypto > @@ -390,6 +394,52 @@ qat_sym_process_response(void **op, uint8_t *resp, > void *op_cookie, > return 1; > } >=20 > +static __rte_always_inline int > +qat_sym_process_response_gen_lce(void **op, uint8_t *resp, > + void *op_cookie __rte_unused, > + uint64_t *dequeue_err_count __rte_unused) > +{ > + struct icp_qat_fw_comn_resp *resp_msg =3D > + (struct icp_qat_fw_comn_resp *)resp; > + struct rte_crypto_op *rx_op =3D (struct rte_crypto_op *)(uintptr_t) > + (resp_msg->opaque_data); > + struct qat_sym_session *sess; > + > +#if RTE_LOG_DP_LEVEL >=3D RTE_LOG_DEBUG > + QAT_DP_HEXDUMP_LOG(DEBUG, "qat_response:", (uint8_t *)resp_msg, > + sizeof(struct icp_qat_fw_comn_resp)); > +#endif > + > + sess =3D CRYPTODEV_GET_SYM_SESS_PRIV(rx_op->sym->session); > + > + rx_op->status =3D RTE_CRYPTO_OP_STATUS_SUCCESS; > + > + if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=3D > + > ICP_QAT_FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET( > + resp_msg->comn_hdr.comn_status)) > + rx_op->status =3D RTE_CRYPTO_OP_STATUS_NOT_PROCESSED; > + > + else if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=3D > + ICP_QAT_FW_COMN_RESP_INVALID_PARAM_STAT_GET( > + resp_msg->comn_hdr.comn_status)) > + rx_op->status =3D RTE_CRYPTO_OP_STATUS_INVALID_ARGS; > + > + if (sess->qat_dir =3D=3D ICP_QAT_HW_CIPHER_DECRYPT) { > + if (ICP_QAT_FW_LA_VER_STATUS_FAIL =3D=3D > + ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET( > + resp_msg->comn_hdr.comn_status)) > + rx_op->status =3D > RTE_CRYPTO_OP_STATUS_AUTH_FAILED; > + } > + > + *op =3D (void *)rx_op; > + > + /* > + * return 1 as dequeue op only move on to the next op > + * if one was ready to return to API > + */ > + return 1; > +} > + > int > qat_sym_configure_dp_ctx(struct rte_cryptodev *dev, uint16_t qp_id, > struct rte_crypto_raw_dp_ctx *raw_dp_ctx, > @@ -455,7 +505,13 @@ qat_sym_preprocess_requests(void **ops > __rte_unused, >=20 > static inline void > qat_sym_process_response(void **op __rte_unused, uint8_t *resp > __rte_unused, > - void *op_cookie __rte_unused) > + void *op_cookie __rte_unused, uint64_t *dequeue_err_count > __rte_unused) > +{ > +} > + > +static inline void > +qat_sym_process_response_gen_lce(void **op __rte_unused, uint8_t *resp > __rte_unused, > + void *op_cookie __rte_unused, uint64_t *dequeue_err_count > __rte_unused) > { > } >=20 > diff --git a/drivers/crypto/qat/qat_sym_session.c > b/drivers/crypto/qat/qat_sym_session.c > index 9f4f6c3d93..8f50b61365 100644 > --- a/drivers/crypto/qat/qat_sym_session.c > +++ b/drivers/crypto/qat/qat_sym_session.c > @@ -136,6 +136,9 @@ qat_sym_cd_auth_set(struct qat_sym_session *cdesc, > static void > qat_sym_session_init_common_hdr(struct qat_sym_session *session); >=20 > +static void > +qat_sym_session_init_gen_lce_hdr(struct qat_sym_session *session); > + > /* Req/cd init functions */ >=20 > static void > @@ -738,6 +741,12 @@ qat_sym_session_set_parameters(struct rte_cryptodev > *dev, > session->qat_cmd); > return -ENOTSUP; > } > + > + if (qat_dev_gen =3D=3D QAT_GEN_LCE) { > + qat_sym_session_init_gen_lce_hdr(session); > + return 0; > + } > + > qat_sym_session_finalize(session); >=20 > return qat_sym_gen_dev_ops[qat_dev_gen].set_session((void *)dev, > @@ -1016,6 +1025,12 @@ qat_sym_session_configure_aead(struct > rte_cryptodev *dev, > dev->data->dev_private; > enum qat_device_gen qat_dev_gen =3D > internals->qat_dev->qat_dev_gen; > + if (qat_dev_gen =3D=3D QAT_GEN_LCE) { > + struct icp_qat_fw_la_bulk_req *req_tmpl =3D &session->fw_req; > + struct lce_key_buff_desc *key_buff =3D &req_tmpl->key_buff; > + > + key_buff->keybuff =3D session->key_paddr; > + } >=20 > /* > * Store AEAD IV parameters as cipher IV, > @@ -1079,9 +1094,15 @@ qat_sym_session_configure_aead(struct > rte_cryptodev *dev, > } >=20 > if (session->is_single_pass) { > - if (qat_sym_cd_cipher_set(session, > + if (qat_dev_gen !=3D QAT_GEN_LCE) { > + if (qat_sym_cd_cipher_set(session, > aead_xform->key.data, aead_xform- > >key.length)) > - return -EINVAL; > + return -EINVAL; > + } else { > + session->auth_key_length =3D aead_xform->key.length; > + memcpy(session->key_array, aead_xform->key.data, > + aead_xform- > >key.length); > + } > } else if ((aead_xform->op =3D=3D RTE_CRYPTO_AEAD_OP_ENCRYPT && > aead_xform->algo =3D=3D RTE_CRYPTO_AEAD_AES_GCM) || > (aead_xform->op =3D=3D RTE_CRYPTO_AEAD_OP_DECRYPT > && > @@ -1970,6 +1991,43 @@ qat_sym_session_init_common_hdr(struct > qat_sym_session *session) >=20 > ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER); > } >=20 > +static void > +qat_sym_session_init_gen_lce_hdr(struct qat_sym_session *session) > +{ > + struct icp_qat_fw_la_bulk_req *req_tmpl =3D &session->fw_req; > + struct icp_qat_fw_comn_req_hdr *header =3D &req_tmpl->comn_hdr; > + > + /* > + * GEN_LCE specifies separate command id for AEAD operations but > Cryptodev > + * API processes AEAD operations as Single pass Crypto operations. > + * Hence even for GEN_LCE, Session Algo Command ID is CIPHER. > + * Note, however Session Algo Mode is AEAD. > + */ > + header->service_cmd_id =3D ICP_QAT_FW_LA_CMD_AEAD; > + header->service_type =3D ICP_QAT_FW_COMN_REQ_CPM_FW_LA; > + header->hdr_flags =3D > + > ICP_QAT_FW_COMN_HDR_FLAGS_BUILD_GEN_LCE(ICP_QAT_FW_COM > N_REQ_FLAG_SET, > + ICP_QAT_FW_COMN_GEN_LCE_DESC_LAYOUT); > + header->comn_req_flags =3D > + > ICP_QAT_FW_COMN_FLAGS_BUILD_GEN_LCE(QAT_COMN_PTR_TYPE_ > SGL, > + QAT_COMN_KEY_BUFFER_USED); > + > + ICP_QAT_FW_SYM_AEAD_ALGO_SET(header->serv_specif_flags, > + QAT_LA_CRYPTO_AEAD_AES_GCM_GEN_LCE); > + ICP_QAT_FW_SYM_IV_SIZE_SET(header->serv_specif_flags, > + ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS); > + ICP_QAT_FW_SYM_IV_IN_DESC_FLAG_SET(header->serv_specif_flags, > + ICP_QAT_FW_SYM_IV_IN_DESC_VALID); > + > + if (session->qat_dir =3D=3D ICP_QAT_HW_CIPHER_DECRYPT) { > + ICP_QAT_FW_SYM_DIR_FLAG_SET(header->serv_specif_flags, > + ICP_QAT_HW_CIPHER_DECRYPT); > + } else { > + ICP_QAT_FW_SYM_DIR_FLAG_SET(header->serv_specif_flags, > + ICP_QAT_HW_CIPHER_ENCRYPT); > + } > +} > + > int qat_sym_cd_cipher_set(struct qat_sym_session *cdesc, > const uint8_t *cipherkey, > uint32_t cipherkeylen) > diff --git a/drivers/crypto/qat/qat_sym_session.h > b/drivers/crypto/qat/qat_sym_session.h > index 9209e2e8df..958af03405 100644 > --- a/drivers/crypto/qat/qat_sym_session.h > +++ b/drivers/crypto/qat/qat_sym_session.h > @@ -111,10 +111,16 @@ struct qat_sym_session { > enum icp_qat_hw_auth_op auth_op; > enum icp_qat_hw_auth_mode auth_mode; > void *bpi_ctx; > - struct qat_sym_cd cd; > + union { > + struct qat_sym_cd cd; > + uint8_t key_array[32]; > + }; > uint8_t prefix_state[QAT_PREFIX_TBL_SIZE] __rte_cache_aligned; > uint8_t *cd_cur_ptr; > - phys_addr_t cd_paddr; > + union { > + phys_addr_t cd_paddr; > + phys_addr_t key_paddr; > + }; > phys_addr_t prefix_paddr; > struct icp_qat_fw_la_bulk_req fw_req; > uint8_t aad_len; > -- > 2.25.1