From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CFCB74410F; Thu, 30 May 2024 14:02:53 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 91F9240608; Thu, 30 May 2024 14:02:53 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 628B9402E4 for ; Thu, 30 May 2024 14:02:52 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 44UAQ3iY022202; Thu, 30 May 2024 05:02:50 -0700 Received: from nam12-bn8-obe.outbound.protection.outlook.com (mail-bn8nam12lp2168.outbound.protection.outlook.com [104.47.55.168]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3yeqpx0atg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 30 May 2024 05:02:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VT0DxhMqct7tzr/uEMaF119xvZZxiRIzOFPzaG5vz8OfVLTyseBpZvlgdiFt5kbOEvA37z6CVU5tU6mOTwUCdBt6rD4dpjdBo9amginn3Wo510IpPQFupnnj5illrlAuFuOU7Uf1PK3V8BSCO2b9Aw4uC0b+YYsfRpSYK3BZKiwZn+rMuzAuuakSweifrnAdobGrBVIkCVlYDErAbDBEvFkoLXu1HxLaWG11adVFA9SBahgijn9Y4td8T7KbqTnFBcXQ3jz/x6IcpggvT8JrzFdRCrI2/wWQaxhUGtQ8pi1JsvOamuBYcUu9YuY7pY5QGtaphjXM/3GyLy98uKzXKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=r3UaPDmh/CowL5x+AA7p6UpelmJLDkiM+PPWmPswJp4=; b=KXcw7hC15DBR2RVeu7OEbWwvhRmOoGasDu48YtJrmRABsc8eo1Ft05jjUXOy7d+tM+iWt6Wo+YUvwHwGIDsCijikfGWbQQsLt3dIWt6PSP1vGdT3/28XN96aj+zfL5/p2+s9t2nsNM5znE/WPU1k/eMtbJoEktjefWpH8YSrJqxDOOECCkpAZD3V3E8ws2tJiz51Sed2xCbhgv56HoZrTjcV+pTbRMgEZS4LoFICd0SRlzN+clKeckjuiN1e9kHoYe7VIfyUomUiGUeuuhrw1aORDb7VZU1mnTZvrw4XSKXucyOxjrrwfj17TuRhTU4law59AxyNgCJ6aLVi3HBu1g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=marvell.com; dmarc=pass action=none header.from=marvell.com; dkim=pass header.d=marvell.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=r3UaPDmh/CowL5x+AA7p6UpelmJLDkiM+PPWmPswJp4=; b=bx3zLcrz8lOQ2EiBeiVHtldCD0t66o3fa08OIazET7V2g62OLWcz7r07AxUbXnGg2pTZ3TM53fR/7MNaDv/zCw+Hicwvp87dReS0BVVyCkTo0Pf9Sgz00MgvVIiy/zjHje06VdQPnkWUlHQwAh8pc7NBH/WP1wf/ptW/QMNIvtQ= Received: from CO6PR18MB4484.namprd18.prod.outlook.com (2603:10b6:5:359::9) by CO1PR18MB4572.namprd18.prod.outlook.com (2603:10b6:303:ff::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.21; Thu, 30 May 2024 12:02:46 +0000 Received: from CO6PR18MB4484.namprd18.prod.outlook.com ([fe80::3c98:dd36:4897:a51d]) by CO6PR18MB4484.namprd18.prod.outlook.com ([fe80::3c98:dd36:4897:a51d%4]) with mapi id 15.20.7633.018; Thu, 30 May 2024 12:02:46 +0000 From: Akhil Goyal To: Andrew Boyer , "dev@dpdk.org" Subject: RE: [EXTERNAL] [PATCH v2 1/9] crypto/ionic: introduce AMD Pensando ionic crypto driver Thread-Topic: [EXTERNAL] [PATCH v2 1/9] crypto/ionic: introduce AMD Pensando ionic crypto driver Thread-Index: AQHamzwYS2OdpCB80EOongcJ/AOFFbGv0Bsg Date: Thu, 30 May 2024 12:02:46 +0000 Message-ID: References: <20240419195310.21432-1-andrew.boyer@amd.com> <20240430202144.49899-1-andrew.boyer@amd.com> <20240430202144.49899-2-andrew.boyer@amd.com> In-Reply-To: <20240430202144.49899-2-andrew.boyer@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: CO6PR18MB4484:EE_|CO1PR18MB4572:EE_ x-ms-office365-filtering-correlation-id: df97cad0-876e-4448-552c-08dc80a06b61 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230031|376005|366007|1800799015|38070700009; x-microsoft-antispam-message-info: =?us-ascii?Q?jM9/eS95Cqjck4/b994vwtqQFDYQVngYxbAWy0gSJPiGHRMyCkZzIuKPiWJH?= =?us-ascii?Q?+E+uWsbfHKQA+bcjAOoF524PAGGdh8NmZRMFM7W8X23yWt1vg5QptL7pKbwG?= =?us-ascii?Q?njbm356ldBBujf5FeRpB9zMQGYcm7YuN7WKkrs49GhJrKZav57SN7XceEZXk?= =?us-ascii?Q?l3L3QdHV2Uh++y8PA5nUIHbxKZKEcsViPlA6lyKjD815pc6NtmfxMCRhg+hY?= =?us-ascii?Q?0hrTY5mO4xW4ay2toWkFcwIXbU+2nCyxccMcaNn6gpX3NMJHVdpGnDPbmi4m?= =?us-ascii?Q?XsWX+Z7Sp3YfHZB/D/mpVDogcKQp81xcq4uAjxlJqnONmq/IE9I3cTYJAYrE?= =?us-ascii?Q?XYku+GXk9L1Ktd6Bzd2lxDQKFdz4GUHeun6Si2uEU8JbIwj+s0rcaFScPBFk?= =?us-ascii?Q?Zv3d10GPBVS82K0X3Ebhd0nezj1rQ0YI1Gn9D8rBu1wd7dqI8wmbP1FmprMz?= =?us-ascii?Q?LDiuYFnvoS3eFURqz3f0QCj6erA19HzFhEYygsvy7EI4E1oe7hLRdBuX+5tw?= =?us-ascii?Q?ToMrZd4xNkKPIy06XZgx5mnMDwkbrIFa+qp0pBN5xn/AbXw85S1x2D0V4znX?= =?us-ascii?Q?0DhFkT2RExtuhdgzRIh8Ser44sCCHbJhIKmh1bqomvgCpbZ7My0LxzOPKqSk?= =?us-ascii?Q?08rGl0i2U48rff4v+hsxOJe46rGBLYljHSs4INHEAMNo2GJcunBjxuTTBvzw?= =?us-ascii?Q?5jrweh/tuj9vq0t5kmnevlB/KGuOMs4jPaLK+EKRcV7s5z42lTjpL+Dy4ZNk?= =?us-ascii?Q?svx7R/lQJ33if7LqHoJKiRy9XTwuI6tFpo76zkO9jTjM8Z9YDU7ONbATcIB4?= =?us-ascii?Q?uuU67Noh1fgt/WI4IzS6mMUEbAbYvocP+iEzJ4MT1KyS467XwPvU/u9bW04l?= =?us-ascii?Q?yIOS7PB2CQe156I5p26pxxL0g6nroN3XifV6bqSThRFf+Xo3FtGB20Cgx+2u?= =?us-ascii?Q?JPST2s5H0EZk+7aWVfjvUIXHn93FLTJRADf0HLpSdOMg9cJB/pP00iqGT/7/?= =?us-ascii?Q?cmMPRdgLdgX3lAup2ZSjyFxrDRznAVv40gcupk2OrKAyHO+xopzGzwM9OMlz?= =?us-ascii?Q?L9Amfop9yUpzrDzVRChkayLL/gVNO1S4jnvdlMfppVHK5vZxbrerP2eUeVvQ?= =?us-ascii?Q?HxATCXHR0afzh6fdUtWQyqVa06yRtQcxAASS6lt4UGklwCo/czpwwlk1EyEY?= =?us-ascii?Q?Rk2furSxX8D/eSGih3xwCDR6RcLd5FTgY+YKUYxnTH28sX582KpxSjX0rejH?= =?us-ascii?Q?5ON0S62AtfGrFE1CRJHEc2LSgNhjCMvl4gs3CKYktJtP2KS2fiGas7RadOuD?= =?us-ascii?Q?EtaSp2qCmgQuodHbfj3/kUOU0WTMi+qJTKy3Gls2f7K7Sg=3D=3D?= x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:CO6PR18MB4484.namprd18.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(376005)(366007)(1800799015)(38070700009); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?4nTUphx3pFPfbq4so2PT8ScbLTxcLlhwUa+BOvIs6RsjlHlRroQWX5TJAdFS?= =?us-ascii?Q?U3iTsJQlsuZfVXVFGmgHxojHwkygkjupXGkzaFR1l8jLY6m1jfQ8rlnOIERi?= =?us-ascii?Q?88lAiLiUz7wqAsmXLRPWOMrbfSjE9Bm+UyI8QrTASB49LTNcsQbONQ/s6pIP?= =?us-ascii?Q?kvRyGCrENtfxrR6bZQVjc5ibSVKqe9QGUu8CMcbmuhXGPm+jaZ1Za2z9tQIn?= =?us-ascii?Q?Z+koXnCv0X2Dz8LLBpOQe0O270NqtBdVfJXDflfSVBlcl0l0gdak1nF9vsKM?= =?us-ascii?Q?OqO32OeVr4J0HBFjcMLJr/RwHPqQ55TqGoVGajL2f4e+12eIRvnwFky+t4/e?= =?us-ascii?Q?ITWWkUwe8S9xo2SmcvgqUj0zDrNU6XgrWBy/Y787eZx+uW8D/ohqO0xiwzLc?= =?us-ascii?Q?v2T4YmVYDivsSZmRu/yO40ate8eETX/QRzw4ZAWF0+fUZEn2H9+ZwFH//N1N?= =?us-ascii?Q?RAxCK9iUiKnnO/KyRi8ZSU/f1Tx1wJ/ysNpCkMO/FcG4PC6M7eQSk+gGF0RF?= =?us-ascii?Q?q4nm5RO02kcFNGoIDb7d9WpMdw1DAEvXf0Ep0bwYeztEzw8huXQ0gW2Y6E0O?= =?us-ascii?Q?QR6D2mne9+qrOSphB9OSN8dw8Ij6pIC+CQUoZC9KLvIhzSQcYdLFX3Y7vHKi?= =?us-ascii?Q?W60RkviDReaIpwLTWIoEkt3iGFLdpEaRRyGBmvdDNk/6GsKFvqtYY2TV1LqW?= =?us-ascii?Q?KCOMnQ/PQZpSop81XCJoPk05a1mQs/tQXGf93+jbk2vwiuyUCyk8uQ3WNQec?= =?us-ascii?Q?4Kv3vepM9igA+fPxaNah0rv0E1rOP2vW6UfFJZQh8g7kZBpSKrmIb4PV4+fI?= =?us-ascii?Q?RYnup7rpFlkzKxeMm0x6SFnPMIpeXRw3Ji21Y9AUyXuBQGBju3VHe//rgvWW?= =?us-ascii?Q?L7xhcwYfGY8Bp3MmHgcib3TaNAlpDkuL8c+vII8fWhzC7IbXJNNLTgHl9LAH?= =?us-ascii?Q?brzX/hMFjONyFzxsne8iQb/q1jqW9rNgXtE8RVvug/GAc7VAUJsA3qNzToDH?= =?us-ascii?Q?KeTUF4S8hE8ekEvTUyBr+zn1F/f1D0l0c2IHFA1SnRV7Jq51Owxsbt/hset3?= =?us-ascii?Q?cXpsaxSdxcnPxGrSNZJz7lMWBSR3x1iL+vT5fa8T/hzPcSFXZDPR+T+hvFw/?= =?us-ascii?Q?lzoF25iRbFoPnobru5jiIY+d/mOOoXFSsDv2E6tAS+xoMBWIZAduQ6ZzXQ2x?= =?us-ascii?Q?lrPhHiTOG4GrX4sN8cyFKvLmo1I0Uar/9ClHEwqwEfqvwt+aL1cOc5ixdA8k?= =?us-ascii?Q?ThaE4jByA85o6qYHzp0+OgiqnFn06X8r2a1ZsS1LOFll7iBbh8Hrkc1BadvQ?= =?us-ascii?Q?sHBtOSfmx95faPc+xlLmDMQznm/b0YdH3BHF9YTV8AGTvQK7IP9ImX+ksKWX?= =?us-ascii?Q?r+u6taCTMItHop+UsUIjEt6jiG3M3w/ykN0omAOg7+ACvlhJ4qabY+erA3nx?= =?us-ascii?Q?BZ9gI60fmgRrxyMBlUICasrylLTeBN8uOyr9vpf4ffM7i0Pg+omGzMfB352p?= =?us-ascii?Q?oNXl48gTTTwf/9wprCSDqDRRbQehwY7L6qAaFYT/zA4B3ZprQOz5el7tgeJv?= =?us-ascii?Q?DZxpgGSYmjSSoXYYVQz3waaR/IwLVCrsTqk79pzc?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO6PR18MB4484.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: df97cad0-876e-4448-552c-08dc80a06b61 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 May 2024 12:02:46.3980 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 1HjbGyiFH9YottBdIEq/smgn8xYd7UhMoNr0zCqsMnnHobfetzaDH7MQd0hs3iNzFECfp9SuhLa+lwUBjIhP9g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR18MB4572 X-Proofpoint-GUID: 3nVONP2lnn5fgam7Y0JACtAY7FzzQqIk X-Proofpoint-ORIG-GUID: 3nVONP2lnn5fgam7Y0JACtAY7FzzQqIk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-30_09,2024-05-28_01,2024-05-17_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > Subject: [EXTERNAL] [PATCH v2 1/9] crypto/ionic: introduce AMD Pensando i= onic > crypto driver >=20 Title should be "crypto/ionic: introduce AMD Pensando driver" Do not repeat words in title. > + > +Device Support > +-------------- > + > +The ionic crypto PMD currently supports running directly on the device's > embedded > +processors. It does not yet support host-side access via PCI. This can be part of driver limitations. > +For help running the PMD, please contact AMD Pensando support. > + > +Runtime Configuration > +--------------------- > + > +None > + > diff --git a/drivers/common/ionic/ionic_common.h > b/drivers/common/ionic/ionic_common.h > index eb4850e24c..c4a15fdf2b 100644 > --- a/drivers/common/ionic/ionic_common.h > +++ b/drivers/common/ionic/ionic_common.h > @@ -32,6 +32,8 @@ struct ionic_dev_bar { >=20 > __rte_internal > void ionic_uio_scan_mnet_devices(void); > +__rte_internal > +void ionic_uio_scan_mcrypt_devices(void); >=20 > __rte_internal > void ionic_uio_get_rsrc(const char *name, int idx, struct ionic_dev_bar = *bar); > diff --git a/drivers/common/ionic/ionic_common_uio.c > b/drivers/common/ionic/ionic_common_uio.c > index e5c73faf96..c647b22eaf 100644 > --- a/drivers/common/ionic/ionic_common_uio.c > +++ b/drivers/common/ionic/ionic_common_uio.c > @@ -23,10 +23,12 @@ >=20 > #define IONIC_MDEV_UNK "mdev_unknown" > #define IONIC_MNIC "cpu_mnic" > +#define IONIC_MCRYPT "cpu_mcrypt" Any specific reason for using the word mcrypt. Can we use mcrypto everywher= e? >=20 > #define IONIC_MAX_NAME_LEN 20 > #define IONIC_MAX_MNETS 5 > -#define IONIC_MAX_DEVICES (IONIC_MAX_MNETS) > +#define IONIC_MAX_MCPTS 1 > +#define IONIC_MAX_DEVICES (IONIC_MAX_MNETS + IONIC_MAX_MCPTS) > #define IONIC_MAX_U16_IDX 0xFFFF > #define IONIC_UIO_MAX_TRIES 32 >=20 > @@ -49,6 +51,7 @@ struct ionic_map_tbl > ionic_mdev_map[IONIC_MAX_DEVICES] =3D { > { "net_ionic2", 2, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK }, > { "net_ionic3", 3, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK }, > { "net_ionic4", 4, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK }, > + { "crypto_ionic0", 5, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK }, > }; >=20 > struct uio_name { > @@ -143,6 +146,49 @@ ionic_uio_scan_mnet_devices(void) > } > } >=20 > +void > +ionic_uio_scan_mcrypt_devices(void) > +{ > + struct ionic_map_tbl *map; > + char devname[IONIC_MAX_NAME_LEN]; > + struct uio_name name_cache[IONIC_MAX_DEVICES]; > + bool done; > + int mdev_idx =3D 0; > + int uio_idx; > + int i; > + static bool scan_done; > + > + if (scan_done) > + return; > + > + scan_done =3D true; > + > + uio_fill_name_cache(name_cache, IONIC_MCRYPT); > + > + for (i =3D IONIC_MAX_MNETS; i < IONIC_MAX_DEVICES; i++) { > + done =3D false; > + > + while (!done) { > + if (mdev_idx > IONIC_MAX_MDEV_SCAN) > + break; > + > + /* Look for a matching mcrypt */ > + snprintf(devname, IONIC_MAX_NAME_LEN, > + IONIC_MCRYPT "%d", mdev_idx); > + uio_idx =3D uio_get_idx_for_devname(name_cache, > devname); > + if (uio_idx >=3D 0) { > + map =3D &ionic_mdev_map[i]; > + map->uio_idx =3D (uint16_t)uio_idx; > + strlcpy(map->mdev_name, devname, > + IONIC_MAX_NAME_LEN); > + done =3D true; > + } > + > + mdev_idx++; > + } > + } > +} > + > static int > uio_get_multi_dev_uionum(const char *name) > { > diff --git a/drivers/common/ionic/version.map > b/drivers/common/ionic/version.map > index 484330c437..db532d4ffc 100644 > --- a/drivers/common/ionic/version.map > +++ b/drivers/common/ionic/version.map > @@ -2,6 +2,7 @@ INTERNAL { > global: >=20 > ionic_uio_scan_mnet_devices; > + ionic_uio_scan_mcrypt_devices; > ionic_uio_get_rsrc; > ionic_uio_rel_rsrc; >=20 > diff --git a/drivers/crypto/ionic/ionic_crypto.h > b/drivers/crypto/ionic/ionic_crypto.h > new file mode 100644 > index 0000000000..86750f0cbd > --- /dev/null > +++ b/drivers/crypto/ionic/ionic_crypto.h > @@ -0,0 +1,92 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright 2021-2024 Advanced Micro Devices, Inc. > + */ > + > +#ifndef _IONIC_CRYPTO_H_ > +#define _IONIC_CRYPTO_H_ > + > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > + > +#include "ionic_common.h" > +#include "ionic_regs.h" > + > +/* Devargs */ > +/* NONE */ > + > +extern int iocpt_logtype; > +#define RTE_LOGTYPE_IOCPT iocpt_logtype > + > +#define IOCPT_PRINT(level, ...) \ > + RTE_LOG_LINE_PREFIX(level, IOCPT, "%s(): ", __func__, __VA_ARGS__) > + > +#define IOCPT_PRINT_CALL() IOCPT_PRINT(DEBUG, " >>") > + > +struct iocpt_dev_bars { > + struct ionic_dev_bar bar[IONIC_BARS_MAX]; > + uint32_t num_bars; > +}; > + > +#define IOCPT_DEV_F_INITED BIT(0) > +#define IOCPT_DEV_F_UP BIT(1) > +#define IOCPT_DEV_F_FW_RESET BIT(2) > + > +/* Combined dev / LIF object */ > +struct iocpt_dev { > + const char *name; > + struct iocpt_dev_bars bars; > + > + const struct iocpt_dev_intf *intf; > + void *bus_dev; > + struct rte_cryptodev *crypto_dev; > + > + uint32_t max_qps; > + uint32_t max_sessions; > + uint16_t state; > + uint8_t driver_id; > + uint8_t socket_id; > + > + uint64_t features; > + uint32_t hw_features; > +}; > + > +struct iocpt_dev_intf { > + int (*setup_bars)(struct iocpt_dev *dev); > + void (*unmap_bars)(struct iocpt_dev *dev); > +}; > + > +static inline int > +iocpt_setup_bars(struct iocpt_dev *dev) > +{ > + if (dev->intf->setup_bars =3D=3D NULL) > + return -EINVAL; > + > + return (*dev->intf->setup_bars)(dev); > +} > + > +int iocpt_probe(void *bus_dev, struct rte_device *rte_dev, > + struct iocpt_dev_bars *bars, const struct iocpt_dev_intf *intf, > + uint8_t driver_id, uint8_t socket_id); > +int iocpt_remove(struct rte_device *rte_dev); > + > +void iocpt_configure(struct iocpt_dev *dev); > +void iocpt_deinit(struct iocpt_dev *dev); > + > +static inline bool > +iocpt_is_embedded(void) > +{ > +#if defined(RTE_LIBRTE_IONIC_PMD_EMBEDDED) > + return true; > +#else > + return false; > +#endif > +} > + > +#endif /* _IONIC_CRYPTO_H_ */ > diff --git a/drivers/crypto/ionic/ionic_crypto_main.c > b/drivers/crypto/ionic/ionic_crypto_main.c > new file mode 100644 > index 0000000000..ecbb1cb161 > --- /dev/null > +++ b/drivers/crypto/ionic/ionic_crypto_main.c > @@ -0,0 +1,148 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright 2021-2024 Advanced Micro Devices, Inc. > + */ > + > +#include > + > +#include > +#include > +#include > + > +#include "ionic_crypto.h" > + > +static int > +iocpt_init(struct iocpt_dev *dev) > +{ > + dev->state |=3D IOCPT_DEV_F_INITED; > + > + return 0; > +} > + > +void > +iocpt_configure(struct iocpt_dev *dev) > +{ > + RTE_SET_USED(dev); > +} > + > +void > +iocpt_deinit(struct iocpt_dev *dev) > +{ > + IOCPT_PRINT_CALL(); > + > + if (!(dev->state & IOCPT_DEV_F_INITED)) > + return; > + > + dev->state &=3D ~IOCPT_DEV_F_INITED; > +} > + > +static int > +iocpt_devargs(struct rte_devargs *devargs, struct iocpt_dev *dev) > +{ > + RTE_SET_USED(devargs); > + RTE_SET_USED(dev); > + > + return 0; > +} > + > +int > +iocpt_probe(void *bus_dev, struct rte_device *rte_dev, > + struct iocpt_dev_bars *bars, const struct iocpt_dev_intf *intf, > + uint8_t driver_id, uint8_t socket_id) > +{ > + struct rte_cryptodev_pmd_init_params init_params =3D { > + "iocpt", > + sizeof(struct iocpt_dev), > + socket_id, > + RTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS > + }; > + struct rte_cryptodev *cdev; > + struct iocpt_dev *dev; > + uint32_t i; > + int err; > + > + /* Multi-process not supported */ It may be highlighted in ionic.rst under limitations. > + if (rte_eal_process_type() !=3D RTE_PROC_PRIMARY) { Print missing here? > + err =3D -EPERM; > + goto err; > + } > + > + cdev =3D rte_cryptodev_pmd_create(rte_dev->name, rte_dev, > &init_params); > + if (cdev =3D=3D NULL) { > + IOCPT_PRINT(ERR, "OOM"); Better to use Out of memory. > + err =3D -ENOMEM; > + goto err; > + } > + > + dev =3D cdev->data->dev_private; > + dev->crypto_dev =3D cdev; > + dev->bus_dev =3D bus_dev; > + dev->intf =3D intf; > + dev->driver_id =3D driver_id; > + dev->socket_id =3D socket_id; > + > + for (i =3D 0; i < bars->num_bars; i++) { > + struct ionic_dev_bar *bar =3D &bars->bar[i]; > + > + IOCPT_PRINT(DEBUG, > + "bar[%u] =3D { .va =3D %p, .pa =3D %#jx, .len =3D %lu }", > + i, bar->vaddr, bar->bus_addr, bar->len); > + if (bar->vaddr =3D=3D NULL) { > + IOCPT_PRINT(ERR, "Null bar found, aborting"); > + err =3D -EFAULT; > + goto err_destroy_crypto_dev; > + } > + > + dev->bars.bar[i].vaddr =3D bar->vaddr; > + dev->bars.bar[i].bus_addr =3D bar->bus_addr; > + dev->bars.bar[i].len =3D bar->len; > + } > + dev->bars.num_bars =3D bars->num_bars; > + > + err =3D iocpt_devargs(rte_dev->devargs, dev); > + if (err !=3D 0) { > + IOCPT_PRINT(ERR, "Cannot parse device arguments"); > + goto err_destroy_crypto_dev; > + } > + > + err =3D iocpt_setup_bars(dev); > + if (err !=3D 0) { > + IOCPT_PRINT(ERR, "Cannot setup BARs: %d, aborting", err); > + goto err_destroy_crypto_dev; > + } > + > + err =3D iocpt_init(dev); > + if (err !=3D 0) { > + IOCPT_PRINT(ERR, "Cannot init device: %d, aborting", err); > + goto err_destroy_crypto_dev; > + } > + > + return 0; > + > +err_destroy_crypto_dev: > + rte_cryptodev_pmd_destroy(cdev); > +err: > + return err; > +} > + > +int > +iocpt_remove(struct rte_device *rte_dev) > +{ > + struct rte_cryptodev *cdev; > + struct iocpt_dev *dev; > + > + cdev =3D rte_cryptodev_pmd_get_named_dev(rte_dev->name); > + if (cdev =3D=3D NULL) { > + IOCPT_PRINT(DEBUG, "Cannot find device %s", rte_dev->name); > + return -ENODEV; > + } > + > + dev =3D cdev->data->dev_private; > + > + iocpt_deinit(dev); > + > + rte_cryptodev_pmd_destroy(cdev); > + > + return 0; > +} > + > +RTE_LOG_REGISTER_DEFAULT(iocpt_logtype, NOTICE); > diff --git a/drivers/crypto/ionic/ionic_crypto_vdev.c > b/drivers/crypto/ionic/ionic_crypto_vdev.c > new file mode 100644 > index 0000000000..a915aa06aa > --- /dev/null > +++ b/drivers/crypto/ionic/ionic_crypto_vdev.c > @@ -0,0 +1,91 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright 2021-2024 Advanced Micro Devices, Inc. > + */ > + > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "ionic_crypto.h" > + > +#define IOCPT_VDEV_DEV_BAR 0 > +#define IOCPT_VDEV_INTR_CTL_BAR 1 > +#define IOCPT_VDEV_INTR_CFG_BAR 2 > +#define IOCPT_VDEV_DB_BAR 3 > +#define IOCPT_VDEV_BARS_MAX 4 > + > +#define IOCPT_VDEV_DEV_INFO_REGS_OFFSET 0x0000 > +#define IOCPT_VDEV_DEV_CMD_REGS_OFFSET 0x0800 > + > +static int > +iocpt_vdev_setup_bars(struct iocpt_dev *dev) > +{ > + IOCPT_PRINT_CALL(); > + > + dev->name =3D rte_vdev_device_name(dev->bus_dev); > + > + return 0; > +} > + > +static void > +iocpt_vdev_unmap_bars(struct iocpt_dev *dev) > +{ > + struct iocpt_dev_bars *bars =3D &dev->bars; > + uint32_t i; > + > + for (i =3D 0; i < IOCPT_VDEV_BARS_MAX; i++) > + ionic_uio_rel_rsrc(dev->name, i, &bars->bar[i]); > +} > + > +static uint8_t iocpt_vdev_driver_id; > +static const struct iocpt_dev_intf iocpt_vdev_intf =3D { > + .setup_bars =3D iocpt_vdev_setup_bars, > + .unmap_bars =3D iocpt_vdev_unmap_bars, > +}; > + > +static int > +iocpt_vdev_probe(struct rte_vdev_device *vdev) > +{ > + struct iocpt_dev_bars bars =3D {}; > + const char *name =3D rte_vdev_device_name(vdev); > + unsigned int i; > + > + IOCPT_PRINT(NOTICE, "Initializing device %s%s", name, > + rte_eal_process_type() =3D=3D RTE_PROC_SECONDARY ? > + " [SECONDARY]" : ""); > + > + ionic_uio_scan_mcrypt_devices(); > + > + for (i =3D 0; i < IOCPT_VDEV_BARS_MAX; i++) > + ionic_uio_get_rsrc(name, i, &bars.bar[i]); > + > + bars.num_bars =3D IOCPT_VDEV_BARS_MAX; > + > + return iocpt_probe((void *)vdev, &vdev->device, > + &bars, &iocpt_vdev_intf, > + iocpt_vdev_driver_id, rte_socket_id()); > +} > + > +static int > +iocpt_vdev_remove(struct rte_vdev_device *vdev) > +{ > + return iocpt_remove(&vdev->device); > +} > + > +static struct rte_vdev_driver rte_vdev_iocpt_pmd =3D { > + .probe =3D iocpt_vdev_probe, > + .remove =3D iocpt_vdev_remove, > +}; > + > +static struct cryptodev_driver rte_vdev_iocpt_drv; > + > +RTE_PMD_REGISTER_VDEV(crypto_ionic, rte_vdev_iocpt_pmd); > +RTE_PMD_REGISTER_CRYPTO_DRIVER(rte_vdev_iocpt_drv, > rte_vdev_iocpt_pmd.driver, > + iocpt_vdev_driver_id); > diff --git a/drivers/crypto/ionic/meson.build b/drivers/crypto/ionic/meso= n.build > new file mode 100644 > index 0000000000..4114e13e53 > --- /dev/null > +++ b/drivers/crypto/ionic/meson.build > @@ -0,0 +1,13 @@ > +# SPDX-License-Identifier: BSD-3-Clause > +# Copyright 2021-2024 Advanced Micro Devices, Inc. > + > +deps +=3D ['bus_vdev'] > +deps +=3D ['common_ionic'] > + > +sources =3D files( > + 'ionic_crypto_main.c', > + 'ionic_crypto_vdev.c', > +) > +name =3D 'ionic_crypto' > + > +includes +=3D include_directories('../../common/ionic') > diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build > index ee5377deff..e799861bb6 100644 > --- a/drivers/crypto/meson.build > +++ b/drivers/crypto/meson.build > @@ -10,6 +10,7 @@ drivers =3D [ > 'cnxk', > 'dpaa_sec', > 'dpaa2_sec', > + 'ionic', > 'ipsec_mb', > 'mlx5', > 'mvsam', > -- > 2.17.1