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Mon, 30 May 2022 07:40:10 +0000 From: Akhil Goyal To: Nicolas Chautru , "dev@dpdk.org" , "trix@redhat.com" , "maxime.coquelin@redhat.com" CC: "thomas@monjalon.net" , "ray.kinsella@intel.com" , "bruce.richardson@intel.com" , "hemant.agrawal@nxp.com" , "hernan.vargas@intel.com" , "david.marchand@redhat.com" Subject: RE: [EXT] [PATCH v6 3/5] baseband/acc100: introduce PMD for ACC101 Thread-Topic: [EXT] [PATCH v6 3/5] baseband/acc100: introduce PMD for ACC101 Thread-Index: AQHYcJyND1cYoUhRVUCW6Z+klHdXA603DLow Date: Mon, 30 May 2022 07:40:10 +0000 Message-ID: References: <1653350912-53876-1-git-send-email-nicolas.chautru@intel.com> <1653526523-68839-1-git-send-email-nicolas.chautru@intel.com> <1653526523-68839-4-git-send-email-nicolas.chautru@intel.com> In-Reply-To: <1653526523-68839-4-git-send-email-nicolas.chautru@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: cf536019-20ce-497a-469c-08da420fa048 x-ms-traffictypediagnostic: PH0PR18MB5116:EE_ x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO6PR18MB4484.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: cf536019-20ce-497a-469c-08da420fa048 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 May 2022 07:40:10.7224 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 030CErpy1l7gMVwitnOMcLQa1ARXOozQZuXSqS8pznn773ezJE9Ski26mkExAZiVw79dSDF22WFpDpJFmTlBgg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR18MB5116 X-Proofpoint-GUID: mOMA0oUReIwTpgkOFSaXPhBZS3YQ2vxU X-Proofpoint-ORIG-GUID: mOMA0oUReIwTpgkOFSaXPhBZS3YQ2vxU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-30_02,2022-05-27_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org >=20 >=20 > Enable Virtual Functions > @@ -167,14 +172,14 @@ queues, priorities, load balance, bandwidth and oth= er > settings necessary for the > device to perform FEC functions. >=20 > This configuration needs to be executed at least once after reboot or PC= I FLR > and can > -be achieved by using the function ``acc100_configure()``, which sets up = the > -parameters defined in ``acc100_conf`` structure. > +be achieved by using the functions ``acc100_configure()`` or > ``acc101_configure()``, I believe the API for user is common now. Right? So why to have two referen= ces? > +which sets up the parameters defined in the compatible ``acc100_conf`` > structure. >=20 > Test Application > ---------------- >=20 > BBDEV provides a test application, ``test-bbdev.py`` and range of test d= ata for > testing > -the functionality of ACC100 5G/4G FEC encode and decode, depending on th= e > device's > +the functionality of the device 5G/4G FEC encode and decode, depending o= n > the device's > capabilities. The test application is located under app->test-bbdev fold= er and > has the > following options: >=20 > @@ -212,7 +217,7 @@ Test Vectors >=20 > In addition to the simple LDPC decoder and LDPC encoder tests, bbdev als= o > provides > a range of additional tests under the test_vectors folder, which may be = useful. > The results > -of these tests will depend on the ACC100 5G/4G FEC capabilities which ma= y > cause some > +of these tests will depend on the device 5G/4G FEC capabilities which ma= y > cause some > testcases to be skipped, but no failure should be reported. >=20 >=20 > @@ -233,3 +238,11 @@ Specifically for the BBDEV ACC100 PMD, the command > below can be used: >=20 > ./pf_bb_config ACC100 -c acc100/acc100_config_vf_5g.cfg > ./test-bbdev.py -e=3D"-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -= b 32 -l 1 -v > ./ldpc_dec_default.data > + > +Specifically for the BBDEV ACC101 PMD, the command below can be used: > + > +.. code-block:: console > + > + ./pf_bb_config ACC101 -c acc101/acc101_config_2vf_4g5g.cfg > + ./test-bbdev.py -e=3D"-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -= b 32 -l 1 - > v ./ldpc_dec_default.data > + > diff --git a/doc/guides/bbdevs/features/acc101.ini > b/doc/guides/bbdevs/features/acc101.ini > new file mode 100644 > index 0000000..0e2c21a > --- /dev/null > +++ b/doc/guides/bbdevs/features/acc101.ini > @@ -0,0 +1,13 @@ > +; > +; Supported features of the 'acc101' bbdev driver. > +; > +; Refer to default.ini for the full list of available PMD features. > +; > +[Features] > +Turbo Decoder (4G) =3D Y > +Turbo Encoder (4G) =3D Y > +LDPC Decoder (5G) =3D Y > +LDPC Encoder (5G) =3D Y > +LLR/HARQ Compression =3D Y > +External DDR Access =3D Y > +HW Accelerated =3D Y > diff --git a/doc/guides/rel_notes/release_22_07.rst > b/doc/guides/rel_notes/release_22_07.rst > index e49cace..1803947 100644 > --- a/doc/guides/rel_notes/release_22_07.rst > +++ b/doc/guides/rel_notes/release_22_07.rst > @@ -104,6 +104,9 @@ New Features > * ``RTE_EVENT_QUEUE_ATTR_WEIGHT`` > * ``RTE_EVENT_QUEUE_ATTR_AFFINITY`` >=20 > +* **Added Intel ACC101 baseband PMD.** > + > + * Added a new baseband PMD for Intel ACC101 device. >=20 > Removed Items > ------------- > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c > b/drivers/baseband/acc100/rte_acc100_pmd.c > index 3fdf17d..6a2123b 100644 > --- a/drivers/baseband/acc100/rte_acc100_pmd.c > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c > @@ -22,6 +22,7 @@ > #include > #include > #include "rte_acc100_pmd.h" > +#include "rte_acc101_pmd.h" >=20 > #ifdef RTE_LIBRTE_BBDEV_DEBUG > RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG); > @@ -1133,7 +1134,10 @@ > /* ACC100 PCI PF address map */ > static struct rte_pci_id pci_id_acc100_pf_map[] =3D { > { > - RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, > RTE_ACC100_PF_DEVICE_ID) > + RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, > RTE_ACC100_PF_DEVICE_ID), > + }, > + { > + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, > RTE_ACC101_PF_DEVICE_ID), > }, > {.device_id =3D 0}, > }; > @@ -1141,7 +1145,10 @@ > /* ACC100 PCI VF address map */ > static struct rte_pci_id pci_id_acc100_vf_map[] =3D { > { > - RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, > RTE_ACC100_VF_DEVICE_ID) > + RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, > RTE_ACC100_VF_DEVICE_ID), > + }, > + { > + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, > RTE_ACC101_VF_DEVICE_ID), > }, > {.device_id =3D 0}, > }; > @@ -1290,7 +1297,7 @@ >=20 > /* Fill in a frame control word for LDPC decoding. */ > static inline void > -acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_= ld > *fcw, > +acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fc= w, > union acc100_harq_layout_data *harq_layout) > { > uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset; > @@ -1414,6 +1421,128 @@ > } > } >=20 > +/* Convert offset to harq index for harq_layout structure */ > +static inline uint32_t hq_index(uint32_t offset) > +{ > + return (offset >> ACC100_HARQ_OFFSET_SHIFT) & > ACC100_HARQ_OFFSET_MASK; > +} > + > +/* Fill in a frame control word for LDPC decoding for ACC101 */ > +static inline void > +acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fc= w, > + union acc100_harq_layout_data *harq_layout) > +{ > + uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset; > + uint32_t harq_index; > + uint32_t l; > + > + fcw->qm =3D op->ldpc_dec.q_m; > + fcw->nfiller =3D op->ldpc_dec.n_filler; > + fcw->BG =3D (op->ldpc_dec.basegraph - 1); > + fcw->Zc =3D op->ldpc_dec.z_c; > + fcw->ncb =3D op->ldpc_dec.n_cb; > + fcw->k0 =3D get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph, > + op->ldpc_dec.rv_index); > + if (op->ldpc_dec.code_block_mode =3D=3D RTE_BBDEV_CODE_BLOCK) > + fcw->rm_e =3D op->ldpc_dec.cb_params.e; > + else > + fcw->rm_e =3D (op->ldpc_dec.tb_params.r < > + op->ldpc_dec.tb_params.cab) ? > + op->ldpc_dec.tb_params.ea : > + op->ldpc_dec.tb_params.eb; > + > + if (unlikely(check_bit(op->ldpc_dec.op_flags, > + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) && > + (op->ldpc_dec.harq_combined_input.length =3D=3D 0))) { > + rte_bbdev_log(WARNING, "Null HARQ input size provided"); > + /* Disable HARQ input in that case to carry forward */ > + op->ldpc_dec.op_flags ^=3D > RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; > + } > + > + fcw->hcin_en =3D check_bit(op->ldpc_dec.op_flags, > + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE); > + fcw->hcout_en =3D check_bit(op->ldpc_dec.op_flags, > + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE); > + fcw->crc_select =3D check_bit(op->ldpc_dec.op_flags, > + RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK); > + fcw->bypass_dec =3D check_bit(op->ldpc_dec.op_flags, > + RTE_BBDEV_LDPC_DECODE_BYPASS); > + fcw->bypass_intlv =3D check_bit(op->ldpc_dec.op_flags, > + RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS); > + if (op->ldpc_dec.q_m =3D=3D 1) { > + fcw->bypass_intlv =3D 1; > + fcw->qm =3D 2; > + } > + fcw->hcin_decomp_mode =3D check_bit(op->ldpc_dec.op_flags, > + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION); > + fcw->hcout_comp_mode =3D check_bit(op->ldpc_dec.op_flags, > + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION); > + fcw->llr_pack_mode =3D check_bit(op->ldpc_dec.op_flags, > + RTE_BBDEV_LDPC_LLR_COMPRESSION); > + harq_index =3D hq_index(op->ldpc_dec.harq_combined_output.offset); > + if (fcw->hcin_en > 0) { > + harq_in_length =3D op->ldpc_dec.harq_combined_input.length; > + if (fcw->hcin_decomp_mode > 0) > + harq_in_length =3D harq_in_length * 8 / 6; > + harq_in_length =3D RTE_MIN(harq_in_length, op->ldpc_dec.n_cb > + - op->ldpc_dec.n_filler); > + /* Alignment on next 64B - Already enforced from HC output */ > + harq_in_length =3D RTE_ALIGN_FLOOR(harq_in_length, 64); > + fcw->hcin_size0 =3D harq_in_length; > + fcw->hcin_offset =3D 0; > + fcw->hcin_size1 =3D 0; > + } else { > + fcw->hcin_size0 =3D 0; > + fcw->hcin_offset =3D 0; > + fcw->hcin_size1 =3D 0; > + } > + > + fcw->itmax =3D op->ldpc_dec.iter_max; > + fcw->itstop =3D check_bit(op->ldpc_dec.op_flags, > + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE); > + fcw->synd_precoder =3D fcw->itstop; > + /* > + * These are all implicitly set > + * fcw->synd_post =3D 0; > + * fcw->so_en =3D 0; > + * fcw->so_bypass_rm =3D 0; > + * fcw->so_bypass_intlv =3D 0; > + * fcw->dec_convllr =3D 0; > + * fcw->hcout_convllr =3D 0; > + * fcw->hcout_size1 =3D 0; > + * fcw->so_it =3D 0; > + * fcw->hcout_offset =3D 0; > + * fcw->negstop_th =3D 0; > + * fcw->negstop_it =3D 0; > + * fcw->negstop_en =3D 0; > + * fcw->gain_i =3D 1; > + * fcw->gain_h =3D 1; > + */ > + if (fcw->hcout_en > 0) { > + parity_offset =3D (op->ldpc_dec.basegraph =3D=3D 1 ? 20 : 8) > + * op->ldpc_dec.z_c - op->ldpc_dec.n_filler; > + k0_p =3D (fcw->k0 > parity_offset) ? > + fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; > + ncb_p =3D fcw->ncb - op->ldpc_dec.n_filler; > + l =3D RTE_MIN(k0_p + fcw->rm_e, INT16_MAX); > + harq_out_length =3D (uint16_t) fcw->hcin_size0; > + harq_out_length =3D RTE_MAX(harq_out_length, l); > + /* Cannot exceed the pruned Ncb circular buffer */ > + harq_out_length =3D RTE_MIN(harq_out_length, ncb_p); > + /* Alignment on next 64B */ > + harq_out_length =3D RTE_ALIGN_CEIL(harq_out_length, 64); > + fcw->hcout_size0 =3D harq_out_length; > + fcw->hcout_size1 =3D 0; > + fcw->hcout_offset =3D 0; > + harq_layout[harq_index].offset =3D fcw->hcout_offset; > + harq_layout[harq_index].size0 =3D fcw->hcout_size0; > + } else { > + fcw->hcout_size0 =3D 0; > + fcw->hcout_size1 =3D 0; > + fcw->hcout_offset =3D 0; > + } > +} > + > /** > * Fills descriptor with data pointers of one block type. > * > @@ -2966,7 +3095,7 @@ > struct acc100_fcw_ld *fcw; > uint32_t seg_total_left; > fcw =3D &desc->req.fcw_ld; > - acc100_fcw_ld_fill(op, fcw, harq_layout); > + q->d->fcw_ld_fill(op, fcw, harq_layout); >=20 > /* Special handling when overusing mbuf */ > if (fcw->rm_e < ACC100_MAX_E_MBUF) > @@ -3033,7 +3162,7 @@ > desc =3D q->ring_addr + desc_idx; > uint64_t fcw_offset =3D (desc_idx << 8) + ACC100_DESC_FCW_OFFSET; > union acc100_harq_layout_data *harq_layout =3D q->d->harq_layout; > - acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout); > + q->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout); >=20 > input =3D op->ldpc_dec.input.data; > h_output_head =3D h_output =3D op->ldpc_dec.hard_output.data; > @@ -4145,9 +4274,19 @@ > dev->dequeue_ldpc_enc_ops =3D acc100_dequeue_ldpc_enc; > dev->dequeue_ldpc_dec_ops =3D acc100_dequeue_ldpc_dec; >=20 > + /* Device variant specific handling */ > + if ((pci_dev->id.device_id =3D=3D RTE_ACC100_PF_DEVICE_ID) || > + (pci_dev->id.device_id =3D=3D RTE_ACC100_VF_DEVICE_ID)) > { > + ((struct acc100_device *) dev->data->dev_private)- > >device_variant =3D ACC100_VARIANT; > + ((struct acc100_device *) dev->data->dev_private)->fcw_ld_fill > =3D acc100_fcw_ld_fill; > + } else { > + ((struct acc100_device *) dev->data->dev_private)- > >device_variant =3D ACC101_VARIANT; > + ((struct acc100_device *) dev->data->dev_private)->fcw_ld_fill > =3D acc101_fcw_ld_fill; > + } > + > ((struct acc100_device *) dev->data->dev_private)->pf_device =3D > - !strcmp(drv->driver.name, > - RTE_STR(ACC100PF_DRIVER_NAME)); > + !strcmp(drv->driver.name, > RTE_STR(ACC100PF_DRIVER_NAME)); > + > ((struct acc100_device *) dev->data->dev_private)->mmio_base =3D > pci_dev->mem_resource[0].addr; >=20 > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h > b/drivers/baseband/acc100/rte_acc100_pmd.h > index 8fea322..39d5f22 100644 > --- a/drivers/baseband/acc100/rte_acc100_pmd.h > +++ b/drivers/baseband/acc100/rte_acc100_pmd.h > @@ -22,6 +22,9 @@ > #define rte_bbdev_log_debug(fmt, ...) > #endif >=20 > +#define ACC100_VARIANT 0 > +#define ACC101_VARIANT 1 Since you are using PCI dev id for identifying the device. Do we still need= above defines? > + > /* ACC100 PF and VF driver names */ > #define ACC100PF_DRIVER_NAME intel_acc100_pf > #define ACC100VF_DRIVER_NAME intel_acc100_vf > @@ -67,6 +70,8 @@ > #define ACC100_HARQ_LAYOUT (64*1024*1024) > /* Assume offset for HARQ in memory */ > #define ACC100_HARQ_OFFSET (32*1024) > +#define ACC100_HARQ_OFFSET_SHIFT 15 > +#define ACC100_HARQ_OFFSET_MASK 0x7ffffff > /* Mask used to calculate an index in an Info Ring array (not a byte off= set) */ > #define ACC100_INFO_RING_MASK (ACC100_INFO_RING_NUM_ENTRIES- > 1) > /* Number of Virtual Functions ACC100 supports */ > @@ -574,6 +579,10 @@ struct __rte_cache_aligned acc100_queue { > struct acc100_device *d; > }; >=20 > +typedef void (*acc10x_fcw_ld_fill_fun_t)(struct rte_bbdev_dec_op *op, > + struct acc100_fcw_ld *fcw, > + union acc100_harq_layout_data *harq_layout); > + > /* Private data structure for each ACC100 device */ > struct acc100_device { > void *mmio_base; /**< Base address of MMIO registers (BAR0) */ > @@ -605,6 +614,8 @@ struct acc100_device { > uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS]; > bool pf_device; /**< True if this is a PF ACC100 device */ > bool configured; /**< True if this ACC100 device is configured */ > + uint16_t device_variant; /**< Device variant */ > + acc10x_fcw_ld_fill_fun_t fcw_ld_fill; /**< 5GUL FCW generation > function */ > }; >=20 > /** > diff --git a/drivers/baseband/acc100/rte_acc101_pmd.h > b/drivers/baseband/acc100/rte_acc101_pmd.h > new file mode 100644 > index 0000000..8f1f4ab > --- /dev/null > +++ b/drivers/baseband/acc100/rte_acc101_pmd.h This file is internal, shouldn't we drop the rte? > @@ -0,0 +1,55 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Intel Corporation > + */ > + > +/* ACC101 PCI vendor & device IDs */ > +#define RTE_ACC101_VENDOR_ID (0x8086) > +#define RTE_ACC101_PF_DEVICE_ID (0x57c4) > +#define RTE_ACC101_VF_DEVICE_ID (0x57c5) > + > +/* Define as 1 to use only a single FEC engine */ > +#ifndef RTE_ACC101_SINGLE_FEC > +#define RTE_ACC101_SINGLE_FEC 0 > +#endif Also the above defines should drop RTE if they are internal symbols. > + > +/* Number of Virtual Functions ACC101 supports */ > +#define ACC101_NUM_VFS 16 > +#define ACC101_NUM_QGRPS 8 > +#define ACC101_NUM_AQS 16 > +/* All ACC101 Registers alignment are 32bits =3D 4B */ > +#define ACC101_BYTES_IN_WORD 4 > + > +#define ACC101_TMPL_PRI_0 0x03020100 > +#define ACC101_TMPL_PRI_1 0x07060504 > +#define ACC101_TMPL_PRI_2 0x0b0a0908 > +#define ACC101_TMPL_PRI_3 0x0f0e0d0c > +#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4) > + > +#define ACC101_NUM_TMPL 32 > +/* Mapping of signals for the available engines */ > +#define ACC101_SIG_UL_5G 0 > +#define ACC101_SIG_UL_5G_LAST 8 > +#define ACC101_SIG_DL_5G 13 > +#define ACC101_SIG_DL_5G_LAST 15 > +#define ACC101_SIG_UL_4G 16 > +#define ACC101_SIG_UL_4G_LAST 19 > +#define ACC101_SIG_DL_4G 27 > +#define ACC101_SIG_DL_4G_LAST 31 > +#define ACC101_NUM_ACCS 5 > +#define ACC101_PF_VAL 2 > + > +/* ACC101 Configuration */ > +#define ACC101_CFG_DMA_ERROR 0x3D7 > +#define ACC101_CFG_AXI_CACHE 0x11 > +#define ACC101_CFG_QMGR_HI_P 0x0F0F > +#define ACC101_CFG_PCI_AXI 0xC003 > +#define ACC101_CFG_PCI_BRIDGE 0x40006033 > +#define ACC101_ENGINE_OFFSET 0x1000 > +#define ACC101_LONG_WAIT 1000 > +#define ACC101_GPEX_AXIMAP_NUM 17 > +#define ACC101_CLOCK_GATING_EN 0x30000 > +#define ACC101_DMA_INBOUND 0x104 > +/* DDR Size per VF - 512MB by default > + * Can be increased up to 4 GB with single PF/VF > + */ > +#define ACC101_HARQ_DDR (512 * 1) > -- > 1.8.3.1