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Mon, 16 May 2022 18:08:57 +0000 From: Akhil Goyal To: Hernan , "dev@dpdk.org" , "trix@redhat.com" CC: "nicolas.chautru@intel.com" , "qi.z.zhang@intel.com" Subject: RE: [EXT] [PATCH v1 2/5] baseband/fpga_5gnr_fec: add FPGA Mutex Thread-Topic: [EXT] [PATCH v1 2/5] baseband/fpga_5gnr_fec: add FPGA Mutex Thread-Index: AQHYY+cTZARhxGZr8UCtUgGNjPI1Ya0h1+OA Date: Mon, 16 May 2022 18:08:57 +0000 Message-ID: References: <20220509201734.946900-1-hernan.vargas@intel.com> <20220509201734.946900-3-hernan.vargas@intel.com> In-Reply-To: <20220509201734.946900-3-hernan.vargas@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 16f7261a-06bb-4597-680f-08da3767252b x-ms-traffictypediagnostic: MN2PR18MB3437:EE_ x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: LL05gTTewFD2hlYfUKCnpDus2vY0TffdCJHMIkQ0VtIifudwVttTGv3XR7FMgJfIqS9Z3iazY8vtKsI6YQbvpVCL74DOcEeyO/b/MOc0farkUW5tWXC2jX8OW585ACHEJQIhFhKJQmG086zDVJI+Z/cP+qwctlB9UMzE78DoSjzXoIPKlBZJ64ZzMfMk6rl0QD5/fwkmp0Zha2yih/vH+JSQtOl5WLlY6BmqhmowBpj09BdyIHW5IcyuOkuIIQxXUFFOveaIe0GQNacgaQ/+kO3uLEkhrmWlLE0PiSdfzBusUkFaqzZFaZcDX6w2wJDs0qsOrbdI9SU973ZGUILlgghh+nPCD910ltD+CxtCjBW2YFFljlfW1MoafE/BzED5hGaMIIGK3KJmIClouiqfGOhnpp9FwpKJslsbTqc6QISuQ9sZbVZ2Fui1KlkCXxLyE9seXt1qg8ikJIVg80A94qe75i0NJi4RHnFxJEkBnL0q2OgtbZ7IwbhXwl+1TQRFLilg02OzYi5RHIG22TWrUkiiCFqgDwgIwwl7a/fkYj35Tti7H/HvCmu5F509UmV6lmOnAEBpzRmxhAadtdSSFQ6IiikZrAfwXFKAZKEf7uHZHvD7wf6FzmaJy2y2wlhh71MMsfIRI25S0jl2BUXT0a+PmO7Q6plUj1olGJM3mAmu7Vh7paQHRfdhP16ojXqy05NQyxJn7QTgdBULKJ4vRA== x-forefront-antispam-report: CIP:255.255.255.255; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO6PR18MB4484.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 16f7261a-06bb-4597-680f-08da3767252b X-MS-Exchange-CrossTenant-originalarrivaltime: 16 May 2022 18:08:57.0482 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Gxuhh8SO7UZcVMJZmrUnXV+86tHgLrGKy31IGAM9bmvtmU7f+vFv2YvWasz3GZp2nHfX4AYBt2mpL1ZUVi1cZg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB3437 X-Proofpoint-ORIG-GUID: FniV39CzjHyVSO7OHLSEnYAGSLZODsXD X-Proofpoint-GUID: FniV39CzjHyVSO7OHLSEnYAGSLZODsXD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-16_15,2022-05-16_02,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > FPGA mutex acquisition and mutex free implemented. Please provide better description to the patches. >=20 > Signed-off-by: Hernan > --- > .../baseband/fpga_5gnr_fec/fpga_5gnr_fec.h | 6 +- > .../fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 77 ++++++++++++++----- > 2 files changed, 62 insertions(+), 21 deletions(-) >=20 > diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h > b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h > index ed8ce26eaa..993cf61974 100644 > --- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h > +++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h > @@ -82,7 +82,9 @@ enum { > FPGA_5GNR_FEC_DDR4_RD_DATA_REGS =3D 0x00000A30, /* len: 8B */ > FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS =3D 0x00000A38, /* len: 1B */ > FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS =3D 0x00000A40, /* len: 1B > */ > - FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS =3D 0x00000A48 /* len: 4B */ > + FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS =3D 0x00000A48, /* len: 4B */ > + FPGA_5GNR_FEC_MUTEX =3D 0x00000A60, /* len: 4B */ > + FPGA_5GNR_FEC_MUTEX_RESET =3D 0x00000A68 /* len: 4B */ > }; >=20 > /* FPGA 5GNR FEC Ring Control Registers */ > @@ -264,6 +266,8 @@ struct __rte_cache_aligned fpga_queue { > uint32_t sw_ring_wrap_mask; > uint32_t irq_enable; /* Enable ops dequeue interrupts if set to 1 */ > uint8_t q_idx; /* Queue index */ > + /** uuid used for MUTEX acquision for DDR */ > + uint16_t ddr_mutex_uuid; > struct fpga_5gnr_fec_device *d; > /* MMIO register of shadow_tail used to enqueue descriptors */ > void *shadow_tail_addr; > diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > index 6737b74901..435b4d90d8 100644 > --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > @@ -1194,11 +1194,45 @@ validate_dec_op(struct rte_bbdev_dec_op *op > __rte_unused) > } > #endif >=20 > +static inline void > +fpga_mutex_acquisition(struct fpga_queue *q) > +{ > + uint32_t mutex_ctrl, mutex_read, cnt =3D 0; > + /* Assign a unique id for the duration of the DDR access */ > + q->ddr_mutex_uuid =3D rand(); > + /* Request and wait for acquisition of the mutex */ > + mutex_ctrl =3D (q->ddr_mutex_uuid << 16) + 1; > + do { > + if (cnt > 0) > + usleep(FPGA_TIMEOUT_CHECK_INTERVAL); > + rte_bbdev_log_debug("Acquiring Mutex for %x\n", > + q->ddr_mutex_uuid); > + fpga_reg_write_32(q->d->mmio_base, > + FPGA_5GNR_FEC_MUTEX, > + mutex_ctrl); > + mutex_read =3D fpga_reg_read_32(q->d->mmio_base, > + FPGA_5GNR_FEC_MUTEX); > + rte_bbdev_log_debug("Mutex %x cnt %d owner %x\n", > + mutex_read, cnt, q->ddr_mutex_uuid); > + cnt++; > + } while ((mutex_read >> 16) !=3D q->ddr_mutex_uuid); > +} > + > +static inline void > +fpga_mutex_free(struct fpga_queue *q) > +{ > + uint32_t mutex_ctrl =3D q->ddr_mutex_uuid << 16; > + fpga_reg_write_32(q->d->mmio_base, > + FPGA_5GNR_FEC_MUTEX, > + mutex_ctrl); > +} > + > static inline int > -fpga_harq_write_loopback(struct fpga_5gnr_fec_device *fpga_dev, > +fpga_harq_write_loopback(struct fpga_queue *q, > struct rte_mbuf *harq_input, uint16_t harq_in_length, > uint32_t harq_in_offset, uint32_t harq_out_offset) > { > + fpga_mutex_acquisition(q); > uint32_t out_offset =3D harq_out_offset; > uint32_t in_offset =3D harq_in_offset; > uint32_t left_length =3D harq_in_length; > @@ -1215,7 +1249,7 @@ fpga_harq_write_loopback(struct > fpga_5gnr_fec_device *fpga_dev, > * Get HARQ buffer size for each VF/PF: When 0x00, there is no > * available DDR space for the corresponding VF/PF. > */ > - reg_32 =3D fpga_reg_read_32(fpga_dev->mmio_base, > + reg_32 =3D fpga_reg_read_32(q->d->mmio_base, > FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS); > if (reg_32 < harq_in_length) { > left_length =3D reg_32; > @@ -1226,46 +1260,48 @@ fpga_harq_write_loopback(struct > fpga_5gnr_fec_device *fpga_dev, > uint8_t *, in_offset); >=20 > while (left_length > 0) { > - if (fpga_reg_read_8(fpga_dev->mmio_base, > + if (fpga_reg_read_8(q->d->mmio_base, > FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) =3D=3D > 1) { > - fpga_reg_write_32(fpga_dev->mmio_base, > + fpga_reg_write_32(q->d->mmio_base, >=20 > FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS, > out_offset); > - fpga_reg_write_64(fpga_dev->mmio_base, > + fpga_reg_write_64(q->d->mmio_base, >=20 > FPGA_5GNR_FEC_DDR4_WR_DATA_REGS, > input[increment]); > left_length -=3D > FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES; > out_offset +=3D > FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES; > increment++; > - fpga_reg_write_8(fpga_dev->mmio_base, > + fpga_reg_write_8(q->d->mmio_base, >=20 > FPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1); > } > } > while (last_transaction > 0) { > - if (fpga_reg_read_8(fpga_dev->mmio_base, > + if (fpga_reg_read_8(q->d->mmio_base, > FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) =3D=3D > 1) { > - fpga_reg_write_32(fpga_dev->mmio_base, > + fpga_reg_write_32(q->d->mmio_base, >=20 > FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS, > out_offset); > last_word =3D input[increment]; > last_word &=3D (uint64_t)(1 << (last_transaction * 4)) > - 1; > - fpga_reg_write_64(fpga_dev->mmio_base, > + fpga_reg_write_64(q->d->mmio_base, >=20 > FPGA_5GNR_FEC_DDR4_WR_DATA_REGS, > last_word); > - fpga_reg_write_8(fpga_dev->mmio_base, > + fpga_reg_write_8(q->d->mmio_base, >=20 > FPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1); > last_transaction =3D 0; > } > } > + fpga_mutex_free(q); > return 1; > } >=20 > static inline int > -fpga_harq_read_loopback(struct fpga_5gnr_fec_device *fpga_dev, > +fpga_harq_read_loopback(struct fpga_queue *q, > struct rte_mbuf *harq_output, uint16_t harq_in_length, > uint32_t harq_in_offset, uint32_t harq_out_offset) > { > + fpga_mutex_acquisition(q); > uint32_t left_length, in_offset =3D harq_in_offset; > uint64_t reg; > uint32_t increment =3D 0; > @@ -1276,7 +1312,7 @@ fpga_harq_read_loopback(struct > fpga_5gnr_fec_device *fpga_dev, > if (last_transaction > 0) > harq_in_length +=3D (8 - last_transaction); >=20 > - reg =3D fpga_reg_read_32(fpga_dev->mmio_base, > + reg =3D fpga_reg_read_32(q->d->mmio_base, > FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS); > if (reg < harq_in_length) { > harq_in_length =3D reg; > @@ -1302,14 +1338,14 @@ fpga_harq_read_loopback(struct > fpga_5gnr_fec_device *fpga_dev, > uint8_t *, harq_out_offset); >=20 > while (left_length > 0) { > - fpga_reg_write_32(fpga_dev->mmio_base, > + fpga_reg_write_32(q->d->mmio_base, > FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS, in_offset); > - fpga_reg_write_8(fpga_dev->mmio_base, > + fpga_reg_write_8(q->d->mmio_base, > FPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 1); > - reg =3D fpga_reg_read_8(fpga_dev->mmio_base, > + reg =3D fpga_reg_read_8(q->d->mmio_base, > FPGA_5GNR_FEC_DDR4_RD_RDY_REGS); > while (reg !=3D 1) { > - reg =3D fpga_reg_read_8(fpga_dev->mmio_base, > + reg =3D fpga_reg_read_8(q->d->mmio_base, > FPGA_5GNR_FEC_DDR4_RD_RDY_REGS); > if (reg =3D=3D FPGA_DDR_OVERFLOW) { > rte_bbdev_log(ERR, > @@ -1317,14 +1353,15 @@ fpga_harq_read_loopback(struct > fpga_5gnr_fec_device *fpga_dev, > return -1; > } > } > - input[increment] =3D fpga_reg_read_64(fpga_dev->mmio_base, > + input[increment] =3D fpga_reg_read_64(q->d->mmio_base, > FPGA_5GNR_FEC_DDR4_RD_DATA_REGS); > left_length -=3D > FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES; > in_offset +=3D FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES; > increment++; > - fpga_reg_write_8(fpga_dev->mmio_base, > + fpga_reg_write_8(q->d->mmio_base, > FPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 0); > } > + fpga_mutex_free(q); > return 1; > } >=20 > @@ -1467,13 +1504,13 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_queue > *q, struct rte_bbdev_dec_op *op, > if (check_bit(dec->op_flags, >=20 > RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE > )) { > - ret =3D fpga_harq_write_loopback(q->d, harq_in, > + ret =3D fpga_harq_write_loopback(q, harq_in, > harq_in_length, harq_in_offset, > harq_out_offset); > } else if (check_bit(dec->op_flags, >=20 > RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE > )) { > - ret =3D fpga_harq_read_loopback(q->d, harq_out, > + ret =3D fpga_harq_read_loopback(q, harq_out, > harq_in_length, harq_in_offset, > harq_out_offset); > dec->harq_combined_output.length =3D harq_in_length; > -- > 2.25.1