From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D6392A0093; Thu, 13 Oct 2022 15:09:36 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8EE8542F73; Thu, 13 Oct 2022 15:09:36 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id EFE4142EAF for ; Thu, 13 Oct 2022 15:09:34 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29DA1I5Q026467; Thu, 13 Oct 2022 06:09:33 -0700 Received: from nam12-mw2-obe.outbound.protection.outlook.com (mail-mw2nam12lp2041.outbound.protection.outlook.com [104.47.66.41]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3k67nqapj7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Oct 2022 06:09:33 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UeGJFYub5li6UT/a4zar8E6xiJF/WecLpfWnVIcEgGg2RnE6ATdvdoaUXhWYkeK/MKIU8jtV4ju/vK/m1Mzk5TBVyFUyMb6J8/OCISwjpJx7h1xCVMYAGYpu944KeB9NyjYTyxsnVBJ9/XyhsFlEcKWv6kH35xHfMRRmTqvjFnuVfSMqCNue/nwZJjzibwc5mjbFFJg/DAs10/NcWI7yPiFsjpdqgE5kGFSI1mFZrIcQEryFh5WRIX/kouSXTjknSo3nYccZtfUa5xrbpSFgp2icIJCvEP9p2BPndmB/+Aou3FVIjwj57RNACp/GZejbqLm7PmjrO+hQT35J6wL1+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sLhkCkSzP6PGgfOC+k8irXrIZ0hz2RpC74OpQaOvD1c=; b=IQL6JtpYKqu6CktLBk4RUf7S7cZI7QuZiDp5+vzDgx30Ib4YS2tCA/kqIOTRui+x9x403jbVLt9UO/cPbDXKuHXJz50tRw//MGZOCchQpdWIyMiMP3mMv/drk7tkUjYal1JiEk9ealt7dDurE7KTgCi61f3PNiopFkisd5DUKiPgUi14Pn+GSy1R+pnxZlh01QGzvichO9ICI/0uHmgvXvkl1+QpKGsm45BXnnPes9XlCNYchFeBv3QsDKLMXSPevdj0Az7qrqMCQ5THujkbfz2veh1ba2QJ8HyCn2s193qbRXcdpHa8dYev6vD3fMfcyQwBy9kcSCE4uEzVoCkMsg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=marvell.com; dmarc=pass action=none header.from=marvell.com; dkim=pass header.d=marvell.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.onmicrosoft.com; s=selector1-marvell-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sLhkCkSzP6PGgfOC+k8irXrIZ0hz2RpC74OpQaOvD1c=; b=nUKmkQK89AcD/SK4REHxNIcRjmhYanNumrjEeGShK0WM/Lu5GcUBahRabBVN2W19HY0tCHSnymPb9ZzXOyWoJBCjQiuWkituCpGfQ9XWYmObwLjAPE9QQVW5qBj4jzRzRvFpbCJ4/lZI2BqlTPfZWwNu21nugvJzVfmXm8jRoG4= Received: from CO6PR18MB4484.namprd18.prod.outlook.com (2603:10b6:5:359::9) by PH0PR18MB4784.namprd18.prod.outlook.com (2603:10b6:510:cd::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.15; Thu, 13 Oct 2022 13:09:26 +0000 Received: from CO6PR18MB4484.namprd18.prod.outlook.com ([fe80::ee27:3b96:a580:ba9e]) by CO6PR18MB4484.namprd18.prod.outlook.com ([fe80::ee27:3b96:a580:ba9e%9]) with mapi id 15.20.5709.019; Thu, 13 Oct 2022 13:09:26 +0000 From: Akhil Goyal To: Hernan Vargas , "dev@dpdk.org" , "trix@redhat.com" , "maxime.coquelin@redhat.com" CC: "nicolas.chautru@intel.com" , "qi.z.zhang@intel.com" Subject: RE: [EXT] [PATCH v3 29/30] baseband/acc100: add workaround for deRM corner cases Thread-Topic: [EXT] [PATCH v3 29/30] baseband/acc100: add workaround for deRM corner cases Thread-Index: AQHY3aNUEdanRksrK0Svsh0Po4iw1q4MTliQ Date: Thu, 13 Oct 2022 13:09:26 +0000 Message-ID: References: <20221012025346.204394-1-hernan.vargas@intel.com> <20221012025346.204394-30-hernan.vargas@intel.com> In-Reply-To: <20221012025346.204394-30-hernan.vargas@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: CO6PR18MB4484:EE_|PH0PR18MB4784:EE_ x-ms-office365-filtering-correlation-id: 1df395f4-4679-4b22-1c38-08daad1c27b1 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: nvesIM0NoCBvo3U3qVFeuteMSlSJwby2lyNtTQHOeRSAJpe5m1hpOJDfj1PN7iUpVsc5zCn8W1S23XmcKMu5VoWN1ILsMIqwnPRUoRgUm7ZwDaJqg4TYKqcGfpn1topL/H22tPZu7/z+bB54fNJ8oTHbJnHyJ5LEPB7MYRWCvO166rpYJ7a0rtafrxl67ckub9rMHgmGUMp6aH97ce79KZzf5M3oS3gFJ/rp+DUl959cRHjKy96iYRp6HBA0CcgHHQKOKDssm4JHmVUFP93agdm0+FazCFKI9X3Z8DnFpHFRrg7JLi1bF0W29WdeZ6juqx9iVkre5CUJwDvRVggfRQ00XM1efBm+cZaz9D47kWaR8aS9TmkcB2rQVoUUxM6QAuAZFd+ZeJxNEV3Gbw2cb5tEwSIi77JkbXhnaI/F3R8vySzY6Z/0MAHHdbbwzFp0rV8gWkK+wSQaE0WVcNF1xLo4U2SbcodtCLNhDQIPj6a0tSyuRDR91bAdhspnpg7sPBEOVIWgTBOs8ST/WnjsJWXH0NqhqusT9w0MHmf2omCrzP0RUMo56oxe5jNYLuMn6aNgUf0ACeyG5N1ljbwmIcEbq2p6eAAhWYiOfU6tYiKJp38a0GZJpnvQzJ0S/b/bYf5ZU7k6jKpbNLYywXqgio9V5YOQI/4rx8DooyRwyaOQghIM+ox6KoN5/ecWHNCKOr0tKa2EjjzlsrMCyBgMJXrNrWutBkxmcti7/Hn9vlQIloC+vZA4uLNyyYp6nCN6l/WofhL+TH+YJMYwdfnKqA== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:CO6PR18MB4484.namprd18.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(366004)(376002)(346002)(396003)(136003)(451199015)(66446008)(55236004)(7696005)(64756008)(33656002)(6506007)(66556008)(4326008)(66476007)(8676002)(54906003)(71200400001)(478600001)(122000001)(76116006)(66946007)(316002)(9686003)(52536014)(38070700005)(186003)(41300700001)(55016003)(83380400001)(86362001)(38100700002)(5660300002)(2906002)(110136005)(8936002)(26005); DIR:OUT; SFP:1101; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?VYR9TfT2Tk0830VOXu3FGCn8uMVczObWRIRtWL/+rEa+9wDRZF70qYNASZB/?= =?us-ascii?Q?qod1pF/RSTfr5qMAmTG5y5I2SaNosXDwgHWx/B3gDE2w/GKR5RABo6FGRtWh?= =?us-ascii?Q?UowLtSKnqrwi1SPBa2/fx7N4hZ9cv4CkYtHx5UsxxSiFQObuTMl/hB+svsLX?= =?us-ascii?Q?V46P2zTiH3srHGS9n1DYH2S4uMm6va5OG7zukCA4HCzo1cTUba/q+5c8KRXM?= =?us-ascii?Q?H9YUnRZ4hcIjxKApe5r1KBWixuyZVRltmFphBcxg0pkV2Sbcwvg8WHuUIw71?= =?us-ascii?Q?cYC4UhrmZTNqsBeiCRxMxB8U9g+athQ3qyqN/fTa1SiucYTVJipRmQhB/nva?= =?us-ascii?Q?JfKIFt62dg9T6CWen0PJI7aHnyE/PH+V+fIia5tBFgrDYe/ZM5pGTX/zKjJA?= =?us-ascii?Q?UNVn3qfDC9rvZHEDZnviYtBxP2hh9ykBvy8o1bbFWhlUZUcWhgQ295Z4jvqa?= =?us-ascii?Q?Ur9aCVawpJZbAK5xDHPBC0NlItaHPE2QdLe0hufgbP7EOCwnunEgCkIhNcj0?= =?us-ascii?Q?XzUdj8uVlbFh+6VcjJgETVndtIKWyGCa6VHSQDGpf0W3quFFl3IdQFHW8PBK?= =?us-ascii?Q?dovJKFOh/qS2tfKy9qjCwFOnjY0dCqaY4lFf2CJxvY0DGnfVKoGTtAvEYCzf?= =?us-ascii?Q?lX4mCxII/HEbBCtmwAeDxZLMRxDafOlX48loGFFY9H2eOQTxK8MyBhU5HiVe?= =?us-ascii?Q?P7AUpUpNghUKTS3GjZxSYvG5Tw2OW9PZHctk9E1l+Wv2M10YQQvBkNGNmPa2?= =?us-ascii?Q?H7uvHjhoY36Y56RijviMHan6VzFCae62yFGNyciN3XunJGm9+54krNt1wohk?= =?us-ascii?Q?Sj+qcWzTFHzqfzv7kVJxLGODGwEV5f53pHdbuN0IUSVbYVC+NC4uXreU9vo8?= =?us-ascii?Q?FFW3d0i23gLq2TSXApJpvtHkhsw4P/90n4V+e13ahGhgrTlDR66rVnS9sQR/?= =?us-ascii?Q?ihHC82M0Zqb07um8oT1A0BNzazYdnit5WaxbjTM3q7yXcv8nE6/DRdJZsKjP?= =?us-ascii?Q?56GBdE7cqzUQ5nsL8M5f0NLuXYWP5ICLbD/VF3h9ow/sX/Eu1DG5HgDQ2Rl8?= =?us-ascii?Q?5cBTRrCeVDQ3dP8zpkl3t1mNxfzu5c9x/DaywiE6z4YDwDXFWI8ctNm8wJup?= =?us-ascii?Q?75a1pxeIVp6PoJBsyC7L1SY76M2Jolqva5mJtV0y8+7yvC2D3AUIRjtFjy1N?= =?us-ascii?Q?VHfOeCMUmT7iJsvIE6n4ITJ9+HBxvo88xQnXPNJwMcYMKQ3Guhgzs3EkWphR?= =?us-ascii?Q?YTkLqxrT5IsKtEdJ+f26nJfqIq6pf6Mx8J2L21Lg8NEHnn/iPJuPn4A3qcVA?= =?us-ascii?Q?Q084WEAGw0QUZyIJYx3M2Z0Bb9t67juBKaXaQkgzZFYXm5+ofisc4VsI5wds?= =?us-ascii?Q?tICzB2Vxrw8KPKbNpzwNPx+l1lqPHmDKv9AQyaUucinaxLmR2SObG8I1Y0sL?= =?us-ascii?Q?9+AMvf+dXX/AeAvo6psI+F7Mx0d+8jnsno2XwVOHYvnCrKAJfrO8HeItzqbX?= =?us-ascii?Q?Jf9bWxfJUGApXTWXasHEeZW8pNxR7VfGgDh0Q45TEZQms2SOIvIfcxoEvJXC?= =?us-ascii?Q?HNXCdeS1BpkaRLvVgPGBE6gm+ySs4Y+mIzMJ/ET8?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO6PR18MB4484.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1df395f4-4679-4b22-1c38-08daad1c27b1 X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Oct 2022 13:09:26.2485 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: q11PGZE5buEyNtbyEMtOASn0zwfJgBtGF3tD/B6p2vLO1hfowFDuJnjWMoa1I9HQU3rZfBR+yvAHwbY/6md3yw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR18MB4784 X-Proofpoint-GUID: bge_vCcf6W6WWJvd5I-VCg-aWxLBcnTc X-Proofpoint-ORIG-GUID: bge_vCcf6W6WWJvd5I-VCg-aWxLBcnTc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-13_08,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > Add function to support de-ratematch pre-processing for SW corner cases. >=20 Please add more meaningful description. Title says adding workaround. You should explain the issue and then what is= done in this patch. > Signed-off-by: Hernan Vargas > --- > drivers/baseband/acc/acc_common.h | 8 ++ > drivers/baseband/acc/meson.build | 21 +++++ > drivers/baseband/acc/rte_acc100_pmd.c | 108 +++++++++++++++++++++++++- > 3 files changed, 134 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/baseband/acc/acc_common.h > b/drivers/baseband/acc/acc_common.h > index 5a9929c336..4b947280c9 100644 > --- a/drivers/baseband/acc/acc_common.h > +++ b/drivers/baseband/acc/acc_common.h > @@ -122,6 +122,14 @@ > #define ACC_HARQ_ALIGN_64B 64 > #define ACC_MAX_ZC 384 >=20 > +/* De-ratematch code rate limitation when padding is required */ > +#define ACC_LIM_03 2 /* 0.03 */ > +#define ACC_LIM_09 6 /* 0.09 */ > +#define ACC_LIM_14 9 /* 0.14 */ > +#define ACC_LIM_21 14 /* 0.21 */ > +#define ACC_LIM_31 20 /* 0.31 */ > +#define ACC_MAX_E (128 * 1024 - 2) > + > /* Helper macro for logging */ > #define rte_acc_log(level, fmt, ...) \ > rte_log(RTE_LOG_ ## level, RTE_LOG_NOTICE, fmt "\n", \ > diff --git a/drivers/baseband/acc/meson.build > b/drivers/baseband/acc/meson.build > index bece3a6e48..b147569d7e 100644 > --- a/drivers/baseband/acc/meson.build > +++ b/drivers/baseband/acc/meson.build > @@ -1,6 +1,27 @@ > # SPDX-License-Identifier: BSD-3-Clause > # Copyright(c) 2020 Intel Corporation >=20 > +# Check for FlexRAN SDK libraries > +dep_dec5g =3D dependency('flexran_sdk_ldpc_decoder_5gnr', required: fals= e) > + > +if dep_dec5g.found() > + ext_deps +=3D cc.find_library('libstdc++', required: true) > + ext_deps +=3D cc.find_library('libirc', required: true) > + ext_deps +=3D cc.find_library('libimf', required: true) > + ext_deps +=3D cc.find_library('libipps', required: true) > + ext_deps +=3D cc.find_library('libsvml', required: true) > + ext_deps +=3D dep_dec5g > + ext_deps +=3D dependency('flexran_sdk_ldpc_encoder_5gnr', required: = true) > + ext_deps +=3D dependency('flexran_sdk_LDPC_ratematch_5gnr', required= : > true) > + ext_deps +=3D dependency('flexran_sdk_rate_dematching_5gnr', require= d: > true) > + ext_deps +=3D dependency('flexran_sdk_turbo', required: true) > + ext_deps +=3D dependency('flexran_sdk_crc', required: true) > + ext_deps +=3D dependency('flexran_sdk_rate_matching', required: true= ) > + ext_deps +=3D dependency('flexran_sdk_common', required: true) > + cflags +=3D ['-DRTE_BBDEV_SDK_AVX2'] > + cflags +=3D ['-DRTE_BBDEV_SDK_AVX512'] > +endif > + > deps +=3D ['bbdev', 'bus_pci'] >=20 > sources =3D files('rte_acc100_pmd.c', 'rte_acc200_pmd.c') > diff --git a/drivers/baseband/acc/rte_acc100_pmd.c > b/drivers/baseband/acc/rte_acc100_pmd.c > index f93fd885a3..44fd0e9ad7 100644 > --- a/drivers/baseband/acc/rte_acc100_pmd.c > +++ b/drivers/baseband/acc/rte_acc100_pmd.c > @@ -24,6 +24,10 @@ > #include "acc100_pmd.h" > #include "acc101_pmd.h" >=20 > +#ifdef RTE_BBDEV_SDK_AVX512 > +#include > +#endif > + > #ifdef RTE_LIBRTE_BBDEV_DEBUG > RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG); > #else > @@ -748,6 +752,14 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t > queue_id, > ret =3D -ENOMEM; > goto free_lb_out; > } > + q->derm_buffer =3D rte_zmalloc_socket(dev->device->driver->name, > + RTE_BBDEV_TURBO_MAX_CB_SIZE * 10, > + RTE_CACHE_LINE_SIZE, conf->socket); > + if (q->derm_buffer =3D=3D NULL) { > + rte_bbdev_log(ERR, "Failed to allocate derm_buffer memory"); > + ret =3D -ENOMEM; > + goto free_companion_ring_addr; > + } >=20 > /* > * Software queue ring wraps synchronously with the HW when it > reaches > @@ -768,7 +780,7 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t > queue_id, > q_idx =3D acc100_find_free_queue_idx(dev, conf); > if (q_idx =3D=3D -1) { > ret =3D -EINVAL; > - goto free_companion_ring_addr; > + goto free_derm_buffer; > } >=20 > q->qgrp_id =3D (q_idx >> ACC100_GRP_ID_SHIFT) & 0xF; > @@ -796,6 +808,9 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t > queue_id, > dev->data->queues[queue_id].queue_private =3D q; > return 0; >=20 > +free_derm_buffer: > + rte_free(q->derm_buffer); > + q->derm_buffer =3D NULL; > free_companion_ring_addr: > rte_free(q->companion_ring_addr); > q->companion_ring_addr =3D NULL; > @@ -882,6 +897,7 @@ acc100_queue_release(struct rte_bbdev *dev, uint16_t > q_id) > /* Mark the Queue as un-assigned */ > d->q_assigned_bit_map[q->qgrp_id] &=3D (0xFFFFFFFFFFFFFFFF - > (uint64_t) (1 << q->aq_id)); > + rte_free(q->derm_buffer); > rte_free(q->companion_ring_addr); > rte_free(q->lb_in); > rte_free(q->lb_out); > @@ -3102,10 +3118,44 @@ harq_loopback(struct acc_queue *q, struct > rte_bbdev_dec_op *op, > return 1; > } >=20 > +/** Assess whether a work around is required for the deRM corner cases *= / > +static inline bool > +derm_workaround_required(struct rte_bbdev_op_ldpc_dec *ldpc_dec, struct > acc_queue *q) > +{ > + if (!is_acc100(q)) > + return false; > + int32_t e =3D ldpc_dec->cb_params.e; > + int q_m =3D ldpc_dec->q_m; > + int z_c =3D ldpc_dec->z_c; > + int K =3D (ldpc_dec->basegraph =3D=3D 1 ? ACC_K_ZC_1 : ACC_K_ZC_2) > + * z_c; > + > + bool required =3D false; > + if (ldpc_dec->basegraph =3D=3D 1) { > + if ((q_m =3D=3D 4) && (z_c >=3D 320) && (e * ACC_LIM_31 > K * 64)) > + required =3D true; > + else if ((e * ACC_LIM_21 > K * 64)) > + required =3D true; > + } else { > + if (q_m <=3D 2) { > + if ((z_c >=3D 208) && (e * ACC_LIM_09 > K * 64)) > + required =3D true; > + else if ((z_c < 208) && (e * ACC_LIM_03 > K * 64)) > + required =3D true; > + } else if (e * ACC_LIM_14 > K * 64) > + required =3D true; > + } > + if (required) > + rte_bbdev_log(INFO, "Running deRM pre-processing in SW"); > + > + return required; > +} > + > /** Enqueue one decode operations for ACC100 device in CB mode */ > static inline int > enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op > *op, > - uint16_t total_enqueued_cbs, bool same_op) > + uint16_t total_enqueued_cbs, bool same_op, > + struct rte_bbdev_queue_data *q_data) > { > int ret; > if (unlikely(check_bit(op->ldpc_dec.op_flags, > @@ -3163,6 +3213,58 @@ enqueue_ldpc_dec_one_op_cb(struct acc_queue > *q, struct rte_bbdev_dec_op *op, > } else { > struct acc_fcw_ld *fcw; > uint32_t seg_total_left; > + > + if (derm_workaround_required(&op->ldpc_dec, q)) { > + #ifdef RTE_BBDEV_SDK_AVX512 > + struct rte_bbdev_op_ldpc_dec *dec =3D &op->ldpc_dec; > + struct bblib_rate_dematching_5gnr_request derm_req; > + struct bblib_rate_dematching_5gnr_response > derm_resp; > + uint8_t *in; > + > + /* Checking input size is matching with E */ > + if (dec->input.data->data_len < dec->cb_params.e) { > + rte_bbdev_log(ERR, "deRM: Input size > mismatch"); > + return -EFAULT; > + } > + /* Run first deRM processing in SW */ > + in =3D rte_pktmbuf_mtod_offset(dec->input.data, uint8_t > *, in_offset); > + derm_req.p_in =3D (int8_t *) in; > + derm_req.p_harq =3D (int8_t *) q->derm_buffer; > + derm_req.base_graph =3D dec->basegraph; > + derm_req.zc =3D dec->z_c; > + derm_req.ncb =3D dec->n_cb; > + derm_req.e =3D dec->cb_params.e; > + if (derm_req.e > ACC_MAX_E) { > + rte_bbdev_log(WARNING, > + "deRM: E %d > %d max", > + derm_req.e, ACC_MAX_E); > + derm_req.e =3D ACC_MAX_E; > + } > + derm_req.k0 =3D 0; /* Actual output from SDK */ > + derm_req.isretx =3D false; > + derm_req.rvid =3D dec->rv_index; > + derm_req.modulation_order =3D dec->q_m; > + derm_req.start_null_index =3D > + (dec->basegraph =3D=3D 1 ? 22 : 10) > + * dec->z_c - 2 * dec->z_c > + - dec->n_filler; > + derm_req.num_of_null =3D dec->n_filler; > + bblib_rate_dematching_5gnr(&derm_req, &derm_resp); > + /* Force back the HW DeRM */ > + dec->q_m =3D 1; > + dec->cb_params.e =3D dec->n_cb - dec->n_filler; > + dec->rv_index =3D 0; > + rte_memcpy(in, q->derm_buffer, dec->cb_params.e); > + /* Capture counter when pre-processing is used */ > + q_data->queue_stats.enqueue_warn_count++; > + #else > + RTE_SET_USED(q_data); > + rte_bbdev_log(WARNING, > + "Corner case may require deRM pre-processing > in SDK" > + ); > + #endif > + } > + > fcw =3D &desc->req.fcw_ld; > q->d->fcw_ld_fill(op, fcw, harq_layout); >=20 > @@ -3734,7 +3836,7 @@ acc100_enqueue_ldpc_dec_cb(struct > rte_bbdev_queue_data *q_data, > ops[i]->ldpc_dec.n_cb, ops[i]->ldpc_dec.q_m, > ops[i]->ldpc_dec.n_filler, ops[i]- > >ldpc_dec.cb_params.e, > same_op); > - ret =3D enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op); > + ret =3D enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op, > q_data); > if (ret < 0) { > acc_enqueue_invalid(q_data); > break; > -- > 2.37.1