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Fri, 28 Apr 2017 05:27:11 +0000 From: "Sekhar, Ashwin" To: Jianbo Liu CC: "thomas@monjalon.net" , "cristian.dumitrescu@intel.com" , "Jacob, Jerin" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH] sched: enable neon optimizations Thread-Index: AQHSv1ZGFYt9DbzSq0y2Iu/YvIyzwQ== Date: Fri, 28 Apr 2017 05:27:11 +0000 Message-ID: References: <20170427130007.33210-1-ashwin.sekhar@caviumnetworks.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: linaro.org; dkim=none (message not signed) header.d=none;linaro.org; dmarc=none action=none header.from=cavium.com; x-originating-ip: [111.93.218.67] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BLUPR0701MB1713; 7:lbHrqj1F0D1sOxnoeMPS3xTN1bz45BgRlO7SF0rBN4BApc55fGVJ7R8AKYE4kRpC/LRmS3vudlotvdyxEmhqOVyzSywu8J2ewDuk/wC0ywbEy13CJBEC1yg9Y6f1GawVs+js7Jpb6HPcclO1kTSQqTUgp9phE7NGTkEpGmpoJnZcygQpPsbtK5u2JunJhK21rf0wK1SGCqZl8lHXnHyrnRTEGu4dvaKOz7g1vyHrOoTK8h+PsTHEKnrbEVZOh7y82ZuBxjqIInkIo6RBniIGIFe1RSlwGTbyMLqflVmVl9ZXBwwWN3PasWEy1iDZEg/udm16yGaDRK9IKUwxJoxw9w== x-forefront-antispam-report: SFV:SKI; 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SRVR:BLUPR0701MB1713; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1713; x-forefront-prvs: 029174C036 spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: cavium.com X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Apr 2017 05:27:11.3490 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1713 Subject: Re: [dpdk-dev] [PATCH] sched: enable neon optimizations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Apr 2017 05:27:17 -0000 On Friday 28 April 2017 09:20 AM, Jianbo Liu wrote:=0A= > On 27 April 2017 at 21:00, Ashwin Sekhar T K=0A= > wrote:=0A= >> * Enabled CONFIG_RTE_SCHED_VECTOR for arm64=0A= >> * Verified the changes with sched_autotest unit test case=0A= >>=0A= >> Signed-off-by: Ashwin Sekhar T K =0A= >> ---=0A= >> config/defconfig_arm64-armv8a-linuxapp-gcc | 2 +-=0A= >> lib/librte_sched/rte_sched.c | 22 ++++++++++++++++++++++= =0A= >> 2 files changed, 23 insertions(+), 1 deletion(-)=0A= >>=0A= >> diff --git a/config/defconfig_arm64-armv8a-linuxapp-gcc b/config/defconf= ig_arm64-armv8a-linuxapp-gcc=0A= >> index 65888ce..021044a 100644=0A= >> --- a/config/defconfig_arm64-armv8a-linuxapp-gcc=0A= >> +++ b/config/defconfig_arm64-armv8a-linuxapp-gcc=0A= >> @@ -48,4 +48,4 @@ CONFIG_RTE_LIBRTE_FM10K_PMD=3Dn=0A= >> CONFIG_RTE_LIBRTE_SFC_EFX_PMD=3Dn=0A= >> CONFIG_RTE_LIBRTE_AVP_PMD=3Dn=0A= >>=0A= >> -CONFIG_RTE_SCHED_VECTOR=3Dn=0A= >> +CONFIG_RTE_SCHED_VECTOR=3Dy=0A= >=0A= > It's enough to remove this line only, I don't think you must enable it=0A= > explicitly in the armv8a common config.=0A= >=0A= Tried removing this line from armv8a config. But in that case =0A= RTE_SCHED_VECTOR doesn't get defined.=0A= ./config/common_base has "CONFIG_RTE_SCHED_VECTOR=3Dn" as the default =0A= setting. So enabling explicitly is required.=0A= =0A= - Ashwin=0A= =0A= >> diff --git a/lib/librte_sched/rte_sched.c b/lib/librte_sched/rte_sched.c= =0A= >> index 614705d..4ba476a 100644=0A= >> --- a/lib/librte_sched/rte_sched.c=0A= >> +++ b/lib/librte_sched/rte_sched.c=0A= >> @@ -58,6 +58,8 @@=0A= >>=0A= >> #if defined(__SSE4__)=0A= >> #define SCHED_VECTOR_SSE4=0A= >> +#elif defined(RTE_MACHINE_CPUFLAG_NEON)=0A= >> +#define SCHED_VECTOR_NEON=0A= >> #endif=0A= >>=0A= >> #endif=0A= >> @@ -1732,6 +1734,26 @@ grinder_pipe_exists(struct rte_sched_port *port, = uint32_t base_pipe)=0A= >> return 1;=0A= >> }=0A= >>=0A= >> +#elif defined(SCHED_VECTOR_NEON)=0A= >> +=0A= >> +static inline int=0A= >> +grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)=0A= >> +{=0A= >> + uint32x4_t index, pipes;=0A= >> + uint32_t *pos =3D (uint32_t *)port->grinder_base_bmp_pos;=0A= >> +=0A= >> + index =3D vmovq_n_u32(base_pipe);=0A= >> + pipes =3D vld1q_u32(pos);=0A= >> + if (!vminvq_u32(veorq_u32(pipes, index)))=0A= >> + return 1;=0A= >> +=0A= >> + pipes =3D vld1q_u32(pos + 4);=0A= >> + if (!vminvq_u32(veorq_u32(pipes, index)))=0A= >> + return 1;=0A= >> +=0A= >> + return 0;=0A= >> +}=0A= >> +=0A= >> #else=0A= >>=0A= >> static inline int=0A= >> --=0A= >> 2.7.4=0A= >>=0A= >=0A= =0A=