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From: "Verma, Shally" <Shally.Verma@cavium.com>
To: "De Lara Guarch, Pablo" <pablo.de.lara.guarch@intel.com>
CC: "Trahe, Fiona" <fiona.trahe@intel.com>, "dev@dpdk.org" <dev@dpdk.org>,
"Athreya, Narayana Prasad" <NarayanaPrasad.Athreya@cavium.com>, "Challa,
Mahipal" <Mahipal.Challa@cavium.com>, "Gupta, Ashish"
<Ashish.Gupta@cavium.com>, "Sahu, Sunila" <Sunila.Sahu@cavium.com>
Thread-Topic: [PATCH v1 4/7] compress/octeontx: add ops enq deq apis
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Subject: Re: [dpdk-dev] [PATCH v1 4/7] compress/octeontx: add ops enq deq
apis
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HI Pablo
>-----Original Message-----
>From: De Lara Guarch, Pablo [mailto:pablo.de.lara.guarch@intel.com]
>Sent: 20 June 2018 03:48
>To: Verma, Shally <Shally.Verma@cavium.com>
>Cc: Trahe, Fiona <fiona.trahe@intel.com>; dev@dpdk.org; Athreya, Narayana =
Prasad <NarayanaPrasad.Athreya@cavium.com>;
>Challa, Mahipal <Mahipal.Challa@cavium.com>; Gupta, Ashish <Ashish.Gupta@c=
avium.com>; Sahu, Sunila
><Sunila.Sahu@cavium.com>
>Subject: RE: [PATCH v1 4/7] compress/octeontx: add ops enq deq apis
>
>External Email
>
>> -----Original Message-----
>> From: Shally Verma [mailto:shally.verma@caviumnetworks.com]
>> Sent: Tuesday, June 5, 2018 11:35 AM
>> To: De Lara Guarch, Pablo <pablo.de.lara.guarch@intel.com>
>> Cc: Trahe, Fiona <fiona.trahe@intel.com>; dev@dpdk.org;
>> pathreya@caviumnetworks.com; mchalla@caviumnetworks.com; Ashish Gupta
>> <ashish.gupta@caviumnetworks.com>; Sunila Sahu
>> <sunila.sahu@caviumnetworks.com>
>> Subject: [PATCH v1 4/7] compress/octeontx: add ops enq deq apis
>>
>> implement enqueue and dequeue apis
>>
>> Signed-off-by: Ashish Gupta <ashish.gupta@caviumnetworks.com>
>> Signed-off-by: Shally Verma <shally.verma@caviumnetworks.com>
>> Signed-off-by: Sunila Sahu <sunila.sahu@caviumnetworks.com>
>
>...
>
>> --- a/drivers/compress/octeontx/zipvf.h
>> +++ b/drivers/compress/octeontx/zipvf.h
>
>...
>
>> +static inline int
>> +zipvf_prepare_out_buf(struct zip_stream *zstrm, struct rte_comp_op *op)
>> +{
>> + uint32_t offset;
>> + union zip_zptr_s *sg_list =3D NULL;
>> + struct rte_mbuf *m_dst;
>> + union zip_inst_s *inst =3D zstrm->inst;
>> + rte_iova_t iova;
>> +
>> + offset =3D op->src.offset;
>> + m_dst =3D op->m_dst;
>> +
>> + if (m_dst->nb_segs =3D=3D 1) {
>> + /* Prepare direct input data pointer */
>> + inst->s.ds =3D 0;
>> + inst->s.out_ptr_addr.s.addr =3D
>> + rte_pktmbuf_iova_offset(m_dst, offset);
>> + inst->s.totaloutputlength =3D rte_pktmbuf_data_len(m_dst) =
-
>> + op->dst.offset;
>> + inst->s.out_ptr_ctl.s.length =3D inst->s.totaloutputlength=
;
>> + return 0;
>> + }
>> +
>> + ZIP_PMD_ERR("output packet is segmented\n");
>> +
>> + /* Packet is segmented, create gather buffer */
>> + inst->s.ds =3D 1;
>> + iova =3D rte_mempool_virt2iova(zstrm->bufs[OUT_DATA_BUF]);
>> + if (iova & 0xF) {
>> + /* Align it to 16 Byte address */
>> + iova =3D ZIP_ALIGN_ROUNDUP(iova, ZIP_SGPTR_ALIGN);
>> + }
>> +
>> + inst->s.out_ptr_addr.s.addr =3D iova;
>> + inst->s.inp_ptr_ctl.s.length =3D (m_dst->nb_segs < MAX_SG_LEN) ?
>> + (m_dst->nb_segs) : MAX_SG_LEN;
>> +
>> + sg_list =3D (union zip_zptr_s *)iova;
>
>There is a compilation issue on gcc 32 bits:
>
>drivers/compress/octeontx/zipvf.h:260:12: error:
>cast to pointer from integer of different size [-Werror=3Dint-to-pointer-c=
ast]
> sg_list =3D (union zip_zptr_s *)iova;
>
[Shally] Shouldn't rte_iova_t should be defined to 32-bit size for 32-bit m=
achine?
Thanks
Shally