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Thu, 15 Oct 2020 17:20:21 +0000 From: "Singh, Jasvinder" To: "Power, Ciara" , "dev@dpdk.org" CC: "viktorin@rehivetech.com" , "ruifeng.wang@arm.com" , "jerinj@marvell.com" , "drc@linux.vnet.ibm.com" , "Richardson, Bruce" , "Ananyev, Konstantin" , "david.marchand@redhat.com" , Olivier Matz Thread-Topic: [PATCH v7 16/18] net: add checks for max SIMD bitwidth Thread-Index: AQHWowdMBmJOM3PnIEuMPb8VJD9KXqmY6KMg Date: Thu, 15 Oct 2020 17:20:21 +0000 Message-ID: References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> <20201015152259.97562-17-ciara.power@intel.com> In-Reply-To: <20201015152259.97562-17-ciara.power@intel.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-reaction: no-action dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [51.37.138.153] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 2e8c1b12-04b9-477f-fd23-08d8712e986f x-ms-traffictypediagnostic: CY4PR1101MB2136: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CY4PR1101MB2134.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2e8c1b12-04b9-477f-fd23-08d8712e986f X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Oct 2020 17:20:21.1686 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: zqdMPXVYJcPodQOJR7afUVIEkE62JxYY5cm2IGpqopZ9j0L5Wem0SUFGK5Mj4jyRUM8OiADGc80z+zuU4ftbPVmneBMHqTZYPhVJuk/oH94= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1101MB2136 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v7 16/18] net: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Power, Ciara > Sent: Thursday, October 15, 2020 4:23 PM > To: dev@dpdk.org > Cc: viktorin@rehivetech.com; ruifeng.wang@arm.com; jerinj@marvell.com; > drc@linux.vnet.ibm.com; Richardson, Bruce ; > Ananyev, Konstantin ; > david.marchand@redhat.com; Power, Ciara ; > Singh, Jasvinder ; Olivier Matz > > Subject: [PATCH v7 16/18] net: add checks for max SIMD bitwidth >=20 > When choosing a vector path to take, an extra condition must be satisfied= to > ensure the max SIMD bitwidth allows for the CPU enabled path. >=20 > The vector path was initially chosen in RTE_INIT, however this is no long= er > suitable as we cannot check the max SIMD bitwidth at that time. > Default handlers are now chosen on initialisation, these default handlers= are > used the first time the crc calc is called, and they set the suitable han= dlers to > be used going forward. >=20 > Suggested-by: Jasvinder Singh > Suggested-by: Olivier Matz >=20 > Signed-off-by: Ciara Power >=20 > --- > v7: Removed unnecessary log variable. > v6: > - Moved log variable and macro to c file instead of public header. > - Added the max_simd_bitwidth condition check to the recently added > handler helper functions. > - Modified default handlers to follow the approach of the set alg > function. > v4: > - Added default handlers to be set at RTE_INIT time, rather than > choosing scalar handlers. > - Modified logging. > - Updated enum name. > v3: > - Moved choosing vector paths out of RTE_INIT. > - Moved checking max_simd_bitwidth into the set_alg function. > --- > lib/librte_net/rte_net_crc.c | 116 +++++++++++++++++++++++++---------- > 1 file changed, 85 insertions(+), 31 deletions(-) >=20 > diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c = index > 32a3665908..c2ff82bbd6 100644 > --- a/lib/librte_net/rte_net_crc.c > +++ b/lib/librte_net/rte_net_crc.c > @@ -9,6 +9,8 @@ > #include > #include > #include > +#include > +#include >=20 > #include "net_crc.h" >=20 > @@ -22,6 +24,12 @@ > static uint32_t crc32_eth_lut[CRC_LUT_SIZE]; static uint32_t > crc16_ccitt_lut[CRC_LUT_SIZE]; >=20 > +static uint32_t > +rte_crc16_ccitt_default_handler(const uint8_t *data, uint32_t > +data_len); > + > +static uint32_t > +rte_crc32_eth_default_handler(const uint8_t *data, uint32_t data_len); > + > static uint32_t > rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len); >=20 > @@ -31,7 +39,12 @@ rte_crc32_eth_handler(const uint8_t *data, uint32_t > data_len); typedef uint32_t (*rte_net_crc_handler)(const uint8_t *data, > uint32_t data_len); >=20 > -static const rte_net_crc_handler *handlers; > +static rte_net_crc_handler handlers_default[] =3D { > + [RTE_NET_CRC16_CCITT] =3D rte_crc16_ccitt_default_handler, > + [RTE_NET_CRC32_ETH] =3D rte_crc32_eth_default_handler, }; > + > +static const rte_net_crc_handler *handlers =3D handlers_default; >=20 > static const rte_net_crc_handler handlers_scalar[] =3D { > [RTE_NET_CRC16_CCITT] =3D rte_crc16_ccitt_handler, @@ -56,6 +69,14 > @@ static const rte_net_crc_handler handlers_neon[] =3D { }; #endif >=20 > +static uint16_t max_simd_bitwidth; > + > +#define NET_LOG(level, fmt, args...) \ > + rte_log(RTE_LOG_ ## level, libnet_logtype, "%s(): " fmt "\n", \ > + __func__, ## args) > + > +RTE_LOG_REGISTER(libnet_logtype, lib.net, INFO); > + > /* Scalar handling */ >=20 > /** > @@ -155,22 +176,21 @@ static const rte_net_crc_handler * > avx512_vpclmulqdq_get_handlers(void) > { > #ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT > - if (AVX512_VPCLMULQDQ_CPU_SUPPORTED) > + if (AVX512_VPCLMULQDQ_CPU_SUPPORTED && > + max_simd_bitwidth >=3D RTE_SIMD_512) > return handlers_avx512; > #endif > + NET_LOG(INFO, "Requirements not met, can't use AVX512\n"); > return NULL; > } >=20 > -static uint8_t > +static void > avx512_vpclmulqdq_init(void) > { > #ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT > - if (AVX512_VPCLMULQDQ_CPU_SUPPORTED) { > + if (AVX512_VPCLMULQDQ_CPU_SUPPORTED) > rte_net_crc_avx512_init(); > - return 1; > - } > #endif > - return 0; > } >=20 > /* SSE4.2/PCLMULQDQ handling */ > @@ -182,22 +202,21 @@ static const rte_net_crc_handler * > sse42_pclmulqdq_get_handlers(void) > { > #ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT > - if (SSE42_PCLMULQDQ_CPU_SUPPORTED) > + if (SSE42_PCLMULQDQ_CPU_SUPPORTED && > + max_simd_bitwidth >=3D RTE_SIMD_128) > return handlers_sse42; > #endif > + NET_LOG(INFO, "Requirements not met, can't use SSE\n"); > return NULL; > } >=20 > -static uint8_t > +static void > sse42_pclmulqdq_init(void) > { > #ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT > - if (SSE42_PCLMULQDQ_CPU_SUPPORTED) { > + if (SSE42_PCLMULQDQ_CPU_SUPPORTED) > rte_net_crc_sse42_init(); > - return 1; > - } > #endif > - return 0; > } >=20 > /* NEON/PMULL handling */ > @@ -209,22 +228,63 @@ static const rte_net_crc_handler * > neon_pmull_get_handlers(void) > { > #ifdef CC_ARM64_NEON_PMULL_SUPPORT > - if (NEON_PMULL_CPU_SUPPORTED) > + if (NEON_PMULL_CPU_SUPPORTED && > + max_simd_bitwidth >=3D RTE_SIMD_128) > return handlers_neon; > #endif > + NET_LOG(INFO, "Requirements not met, can't use NEON\n"); > return NULL; > } >=20 > -static uint8_t > +static void > neon_pmull_init(void) > { > #ifdef CC_ARM64_NEON_PMULL_SUPPORT > - if (NEON_PMULL_CPU_SUPPORTED) { > + if (NEON_PMULL_CPU_SUPPORTED) > rte_net_crc_neon_init(); > - return 1; > - } > #endif > - return 0; > +} > + > +/* Default handling */ > + > +static uint32_t > +rte_crc16_ccitt_default_handler(const uint8_t *data, uint32_t data_len) > +{ > + handlers =3D NULL; > + if (max_simd_bitwidth =3D=3D 0) > + max_simd_bitwidth =3D rte_get_max_simd_bitwidth(); > + > + handlers =3D avx512_vpclmulqdq_get_handlers(); > + if (handlers !=3D NULL) > + return handlers[RTE_NET_CRC16_CCITT](data, data_len); > + handlers =3D sse42_pclmulqdq_get_handlers(); > + if (handlers !=3D NULL) > + return handlers[RTE_NET_CRC16_CCITT](data, data_len); > + handlers =3D neon_pmull_get_handlers(); > + if (handlers !=3D NULL) > + return handlers[RTE_NET_CRC16_CCITT](data, data_len); > + handlers =3D handlers_scalar; > + return handlers[RTE_NET_CRC16_CCITT](data, data_len); } > + > +static uint32_t > +rte_crc32_eth_default_handler(const uint8_t *data, uint32_t data_len) { > + handlers =3D NULL; > + if (max_simd_bitwidth =3D=3D 0) > + max_simd_bitwidth =3D rte_get_max_simd_bitwidth(); > + > + handlers =3D avx512_vpclmulqdq_get_handlers(); > + if (handlers !=3D NULL) > + return handlers[RTE_NET_CRC32_ETH](data, data_len); > + handlers =3D sse42_pclmulqdq_get_handlers(); > + if (handlers !=3D NULL) > + return handlers[RTE_NET_CRC32_ETH](data, data_len); > + handlers =3D neon_pmull_get_handlers(); > + if (handlers !=3D NULL) > + return handlers[RTE_NET_CRC32_ETH](data, data_len); > + handlers =3D handlers_scalar; > + return handlers[RTE_NET_CRC32_ETH](data, data_len); > } >=20 > /* Public API */ > @@ -233,6 +293,8 @@ void > rte_net_crc_set_alg(enum rte_net_crc_alg alg) { > handlers =3D NULL; > + if (max_simd_bitwidth =3D=3D 0) > + max_simd_bitwidth =3D rte_get_max_simd_bitwidth(); >=20 > switch (alg) { > case RTE_NET_CRC_AVX512: > @@ -270,19 +332,11 @@ rte_net_crc_calc(const void *data, > return ret; > } >=20 > -/* Select highest available crc algorithm as default one */ > +/* Call initialisation helpers for all crc algorithm handlers */ > RTE_INIT(rte_net_crc_init) > { > - enum rte_net_crc_alg alg =3D RTE_NET_CRC_SCALAR; > - > rte_net_crc_scalar_init(); > - > - if (sse42_pclmulqdq_init()) > - alg =3D RTE_NET_CRC_SSE42; > - if (avx512_vpclmulqdq_init()) > - alg =3D RTE_NET_CRC_AVX512; > - if (neon_pmull_init()) > - alg =3D RTE_NET_CRC_NEON; > - > - rte_net_crc_set_alg(alg); > + sse42_pclmulqdq_init(); > + avx512_vpclmulqdq_init(); > + neon_pmull_init(); > } > -- > 2.22.0 Acked-by: Jasvinder Singh