* [PATCH] sched: enable CMAN at runtime
@ 2022-05-11 13:53 Marcin Danilewicz
2022-05-12 13:10 ` [PATCH v2] " Marcin Danilewicz
0 siblings, 1 reply; 27+ messages in thread
From: Marcin Danilewicz @ 2022-05-11 13:53 UTC (permalink / raw)
To: dev, jasvinder.singh, cristian.dumitrescu; +Cc: megha.ajmera
Added changes to enable CMAN (RED or PIE) at init
from profile configuration file.
By default CMAN code is enable but not in use, when
there is no RED or PIE profile configured.
Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
---
config/rte_config.h | 3 -
drivers/net/softnic/rte_eth_softnic_tm.c | 12 --
examples/ip_pipeline/tmgr.c | 4 -
examples/qos_sched/cfg_file.c | 14 +--
examples/qos_sched/cfg_file.h | 2 -
examples/qos_sched/init.c | 4 -
examples/qos_sched/main.h | 2 -
examples/qos_sched/profile.cfg | 130 ++++++++++-----------
examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++
examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++
lib/sched/rte_sched.c | 53 ++-------
lib/sched/rte_sched.h | 1 +
12 files changed, 370 insertions(+), 140 deletions(-)
create mode 100644 examples/qos_sched/profile_pie.cfg
create mode 100644 examples/qos_sched/profile_red.cfg
diff --git a/config/rte_config.h b/config/rte_config.h
index 8eb29c1525..1740a1d053 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -88,9 +88,6 @@
/* rte_power defines */
#define RTE_MAX_LCORE_FREQS 64
-/* rte_sched defines */
-#undef RTE_SCHED_CMAN
-
/* rte_graph defines */
#define RTE_GRAPH_BURST_SIZE 256
#define RTE_LIBRTE_GRAPH_STATS 1
diff --git a/drivers/net/softnic/rte_eth_softnic_tm.c b/drivers/net/softnic/rte_eth_softnic_tm.c
index 6a7766ba1c..3a5fd676e9 100644
--- a/drivers/net/softnic/rte_eth_softnic_tm.c
+++ b/drivers/net/softnic/rte_eth_softnic_tm.c
@@ -420,11 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,
return 0;
}
-#ifdef RTE_SCHED_CMAN
#define WRED_SUPPORTED 1
-#else
-#define WRED_SUPPORTED 0
-#endif
#define STATS_MASK_DEFAULT \
(RTE_TM_STATS_N_PKTS | \
@@ -2300,8 +2296,6 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev, uint32_t tc_id)
return NULL;
}
-#ifdef RTE_SCHED_CMAN
-
static void
wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
{
@@ -2325,12 +2319,6 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
}
}
-#else
-
-#define wred_profiles_set(dev, subport_id)
-
-#endif
-
static struct tm_shared_shaper *
tm_tc_shared_shaper_get(struct rte_eth_dev *dev, struct tm_node *tc_node)
{
diff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c
index b138e885cf..e68e9961be 100644
--- a/examples/ip_pipeline/tmgr.c
+++ b/examples/ip_pipeline/tmgr.c
@@ -17,7 +17,6 @@ static uint32_t n_subport_profiles;
static struct rte_sched_pipe_params
pipe_profile[TMGR_PIPE_PROFILE_MAX];
-#ifdef RTE_SCHED_CMAN
static struct rte_sched_cman_params cman_params = {
.red_params = {
/* Traffic Class 0 Colors Green / Yellow / Red */
@@ -86,7 +85,6 @@ static struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
static uint32_t n_pipe_profiles;
@@ -96,9 +94,7 @@ static const struct rte_sched_subport_params subport_params_default = {
.pipe_profiles = pipe_profile,
.n_pipe_profiles = 0, /* filled at run time */
.n_max_pipe_profiles = RTE_DIM(pipe_profile),
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
};
static struct tmgr_port_list tmgr_port_list;
diff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c
index 450482f07d..efff1dbb01 100644
--- a/examples/qos_sched/cfg_file.c
+++ b/examples/qos_sched/cfg_file.c
@@ -229,13 +229,15 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg,
return 0;
}
-#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p)
{
int j, k;
subport_p->cman_params->cman_mode = cman_p.cman_mode;
+ if (subport_p->cman_params->cman_mode == RTE_SCHED_CMAN_NONE)
+ return;
+
for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
if (subport_p->cman_params->cman_mode ==
RTE_SCHED_CMAN_RED) {
@@ -261,7 +263,6 @@ void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
}
}
}
-#endif
int
cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)
@@ -276,12 +277,14 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
memset(active_queues, 0, sizeof(active_queues));
n_active_queues = 0;
-#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
- .cman_mode = RTE_SCHED_CMAN_RED,
.red_params = { },
};
+ if (cman_params.cman_mode != RTE_SCHED_CMAN_NONE) {
+ cman_params.cman_mode = RTE_SCHED_CMAN_NONE;
+ }
+
if (rte_cfgfile_has_section(cfg, "red")) {
cman_params.cman_mode = RTE_SCHED_CMAN_RED;
@@ -387,7 +390,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
-#endif /* RTE_SCHED_CMAN */
for (i = 0; i < MAX_SCHED_SUBPORTS; i++) {
char sec_name[CFG_NAME_LEN];
@@ -465,9 +467,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
}
-#ifdef RTE_SCHED_CMAN
set_subport_cman_params(subport_params+i, cman_params);
-#endif
}
}
diff --git a/examples/qos_sched/cfg_file.h b/examples/qos_sched/cfg_file.h
index 1a9dce9db5..19df91e7ba 100644
--- a/examples/qos_sched/cfg_file.h
+++ b/examples/qos_sched/cfg_file.h
@@ -12,10 +12,8 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);
int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);
-#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p);
-#endif
int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);
diff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c
index 8a0fb8a374..0afd553283 100644
--- a/examples/qos_sched/init.c
+++ b/examples/qos_sched/init.c
@@ -201,7 +201,6 @@ static struct rte_sched_subport_profile_params
},
};
-#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
.cman_mode = RTE_SCHED_CMAN_RED,
.red_params = {
@@ -271,7 +270,6 @@ struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
{
@@ -281,9 +279,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
.n_pipe_profiles = sizeof(pipe_profiles) /
sizeof(struct rte_sched_pipe_params),
.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
},
};
diff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h
index 915311bac8..76a68f585f 100644
--- a/examples/qos_sched/main.h
+++ b/examples/qos_sched/main.h
@@ -153,9 +153,7 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
extern uint32_t n_active_queues;
extern struct rte_sched_port_params port_params;
-#ifdef RTE_SCHED_CMAN
extern struct rte_sched_cman_params cman_params;
-#endif
extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];
int app_parse_args(int argc, char **argv);
diff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg
index d4b21c0170..db65b0ed01 100644
--- a/examples/qos_sched/profile.cfg
+++ b/examples/qos_sched/profile.cfg
@@ -142,68 +142,68 @@ tc 12 wrr weights = 1 1 1 1
;tc 12 wred inv prob = 10 10 10
;tc 12 wred weight = 9 9 9
-[pie]
-tc 0 qdelay ref = 15
-tc 0 max burst = 150
-tc 0 update interval = 15
-tc 0 tailq th = 64
-
-tc 1 qdelay ref = 15
-tc 1 max burst = 150
-tc 1 update interval = 15
-tc 1 tailq th = 64
-
-tc 2 qdelay ref = 15
-tc 2 max burst = 150
-tc 2 update interval = 15
-tc 2 tailq th = 64
-
-tc 3 qdelay ref = 15
-tc 3 max burst = 150
-tc 3 update interval = 15
-tc 3 tailq th = 64
-
-tc 4 qdelay ref = 15
-tc 4 max burst = 150
-tc 4 update interval = 15
-tc 4 tailq th = 64
-
-tc 5 qdelay ref = 15
-tc 5 max burst = 150
-tc 5 update interval = 15
-tc 5 tailq th = 64
-
-tc 6 qdelay ref = 15
-tc 6 max burst = 150
-tc 6 update interval = 15
-tc 6 tailq th = 64
-
-tc 7 qdelay ref = 15
-tc 7 max burst = 150
-tc 7 update interval = 15
-tc 7 tailq th = 64
-
-tc 8 qdelay ref = 15
-tc 8 max burst = 150
-tc 8 update interval = 15
-tc 8 tailq th = 64
-
-tc 9 qdelay ref = 15
-tc 9 max burst = 150
-tc 9 update interval = 15
-tc 9 tailq th = 64
-
-tc 10 qdelay ref = 15
-tc 10 max burst = 150
-tc 10 update interval = 15
-tc 10 tailq th = 64
-
-tc 11 qdelay ref = 15
-tc 11 max burst = 150
-tc 11 update interval = 15
-tc 11 tailq th = 64
-
-tc 12 qdelay ref = 15
-tc 12 max burst = 150
-tc 12 update interval = 15
-tc 12 tailq th = 64
+;[pie]
+;tc 0 qdelay ref = 15
+;tc 0 max burst = 150
+;tc 0 update interval = 15
+;tc 0 tailq th = 64
+
+;tc 1 qdelay ref = 15
+;tc 1 max burst = 150
+;tc 1 update interval = 15
+;tc 1 tailq th = 64
+
+;tc 2 qdelay ref = 15
+;tc 2 max burst = 150
+;tc 2 update interval = 15
+;tc 2 tailq th = 64
+
+;tc 3 qdelay ref = 15
+;tc 3 max burst = 150
+;tc 3 update interval = 15
+;tc 3 tailq th = 64
+
+;tc 4 qdelay ref = 15
+;tc 4 max burst = 150
+;tc 4 update interval = 15
+;tc 4 tailq th = 64
+
+;tc 5 qdelay ref = 15
+;tc 5 max burst = 150
+;tc 5 update interval = 15
+;tc 5 tailq th = 64
+
+;tc 6 qdelay ref = 15
+;tc 6 max burst = 150
+;tc 6 update interval = 15
+;tc 6 tailq th = 64
+
+;tc 7 qdelay ref = 15
+;tc 7 max burst = 150
+;tc 7 update interval = 15
+;tc 7 tailq th = 64
+
+;tc 8 qdelay ref = 15
+;tc 8 max burst = 150
+;tc 8 update interval = 15
+;tc 8 tailq th = 64
+
+;tc 9 qdelay ref = 15
+;tc 9 max burst = 150
+;tc 9 update interval = 15
+;tc 9 tailq th = 64
+
+;tc 10 qdelay ref = 15
+;tc 10 max burst = 150
+;tc 10 update interval = 15
+;tc 10 tailq th = 64
+
+;tc 11 qdelay ref = 15
+;tc 11 max burst = 150
+;tc 11 update interval = 15
+;tc 11 tailq th = 64
+
+;tc 12 qdelay ref = 15
+;tc 12 max burst = 150
+;tc 12 update interval = 15
+;tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_pie.cfg b/examples/qos_sched/profile_pie.cfg
new file mode 100644
index 0000000000..241f748b33
--- /dev/null
+++ b/examples/qos_sched/profile_pie.cfg
@@ -0,0 +1,142 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+[pie]
+tc 0 qdelay ref = 15
+tc 0 max burst = 150
+tc 0 update interval = 15
+tc 0 tailq th = 64
+
+tc 1 qdelay ref = 15
+tc 1 max burst = 150
+tc 1 update interval = 15
+tc 1 tailq th = 64
+
+tc 2 qdelay ref = 15
+tc 2 max burst = 150
+tc 2 update interval = 15
+tc 2 tailq th = 64
+
+tc 3 qdelay ref = 15
+tc 3 max burst = 150
+tc 3 update interval = 15
+tc 3 tailq th = 64
+
+tc 4 qdelay ref = 15
+tc 4 max burst = 150
+tc 4 update interval = 15
+tc 4 tailq th = 64
+
+tc 5 qdelay ref = 15
+tc 5 max burst = 150
+tc 5 update interval = 15
+tc 5 tailq th = 64
+
+tc 6 qdelay ref = 15
+tc 6 max burst = 150
+tc 6 update interval = 15
+tc 6 tailq th = 64
+
+tc 7 qdelay ref = 15
+tc 7 max burst = 150
+tc 7 update interval = 15
+tc 7 tailq th = 64
+
+tc 8 qdelay ref = 15
+tc 8 max burst = 150
+tc 8 update interval = 15
+tc 8 tailq th = 64
+
+tc 9 qdelay ref = 15
+tc 9 max burst = 150
+tc 9 update interval = 15
+tc 9 tailq th = 64
+
+tc 10 qdelay ref = 15
+tc 10 max burst = 150
+tc 10 update interval = 15
+tc 10 tailq th = 64
+
+tc 11 qdelay ref = 15
+tc 11 max burst = 150
+tc 11 update interval = 15
+tc 11 tailq th = 64
+
+tc 12 qdelay ref = 15
+tc 12 max burst = 150
+tc 12 update interval = 15
+tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_red.cfg b/examples/qos_sched/profile_red.cfg
new file mode 100644
index 0000000000..4486d2799e
--- /dev/null
+++ b/examples/qos_sched/profile_red.cfg
@@ -0,0 +1,143 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+; RED params per traffic class and color (Green / Yellow / Red)
+[red]
+tc 0 wred min = 48 40 32
+tc 0 wred max = 64 64 64
+tc 0 wred inv prob = 10 10 10
+tc 0 wred weight = 9 9 9
+
+tc 1 wred min = 48 40 32
+tc 1 wred max = 64 64 64
+tc 1 wred inv prob = 10 10 10
+tc 1 wred weight = 9 9 9
+
+tc 2 wred min = 48 40 32
+tc 2 wred max = 64 64 64
+tc 2 wred inv prob = 10 10 10
+tc 2 wred weight = 9 9 9
+
+tc 3 wred min = 48 40 32
+tc 3 wred max = 64 64 64
+tc 3 wred inv prob = 10 10 10
+tc 3 wred weight = 9 9 9
+
+tc 4 wred min = 48 40 32
+tc 4 wred max = 64 64 64
+tc 4 wred inv prob = 10 10 10
+tc 4 wred weight = 9 9 9
+
+tc 5 wred min = 48 40 32
+tc 5 wred max = 64 64 64
+tc 5 wred inv prob = 10 10 10
+tc 5 wred weight = 9 9 9
+
+tc 6 wred min = 48 40 32
+tc 6 wred max = 64 64 64
+tc 6 wred inv prob = 10 10 10
+tc 6 wred weight = 9 9 9
+
+tc 7 wred min = 48 40 32
+tc 7 wred max = 64 64 64
+tc 7 wred inv prob = 10 10 10
+tc 7 wred weight = 9 9 9
+
+tc 8 wred min = 48 40 32
+tc 8 wred max = 64 64 64
+tc 8 wred inv prob = 10 10 10
+tc 8 wred weight = 9 9 9
+
+tc 9 wred min = 48 40 32
+tc 9 wred max = 64 64 64
+tc 9 wred inv prob = 10 10 10
+tc 9 wred weight = 9 9 9
+
+tc 10 wred min = 48 40 32
+tc 10 wred max = 64 64 64
+tc 10 wred inv prob = 10 10 10
+tc 10 wred weight = 9 9 9
+
+tc 11 wred min = 48 40 32
+tc 11 wred max = 64 64 64
+tc 11 wred inv prob = 10 10 10
+tc 11 wred weight = 9 9 9
+
+tc 12 wred min = 48 40 32
+tc 12 wred max = 64 64 64
+tc 12 wred inv prob = 10 10 10
+tc 12 wred weight = 9 9 9
diff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c
index ec74bee939..db14934832 100644
--- a/lib/sched/rte_sched.c
+++ b/lib/sched/rte_sched.c
@@ -81,13 +81,11 @@ struct rte_sched_queue {
struct rte_sched_queue_extra {
struct rte_sched_queue_stats stats;
-#ifdef RTE_SCHED_CMAN
RTE_STD_C11
union {
struct rte_red red;
struct rte_pie pie;
};
-#endif
};
enum grinder_state {
@@ -179,7 +177,6 @@ struct rte_sched_subport {
/* Pipe queues size */
uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
-#ifdef RTE_SCHED_CMAN
bool cman_enabled;
enum rte_sched_cman_mode cman;
@@ -188,7 +185,6 @@ struct rte_sched_subport {
struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];
struct rte_pie_config pie_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
};
-#endif
/* Scheduling loop detection */
uint32_t pipe_loop;
@@ -1081,7 +1077,6 @@ rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports)
rte_free(port);
}
-#ifdef RTE_SCHED_CMAN
static int
rte_sched_red_config(struct rte_sched_port *port,
struct rte_sched_subport *s,
@@ -1161,9 +1156,11 @@ rte_sched_cman_config(struct rte_sched_port *port,
else if (params->cman_params->cman_mode == RTE_SCHED_CMAN_PIE)
return rte_sched_pie_config(port, s, params, n_subports);
+ else if (params->cman_params->cman_mode == RTE_SCHED_CMAN_NONE)
+ return 1;
+
return -EINVAL;
}
-#endif
int
rte_sched_subport_config(struct rte_sched_port *port,
@@ -1254,19 +1251,20 @@ rte_sched_subport_config(struct rte_sched_port *port,
s->n_pipe_profiles = params->n_pipe_profiles;
s->n_max_pipe_profiles = params->n_max_pipe_profiles;
-#ifdef RTE_SCHED_CMAN
+ s->cman_enabled = false;
+
if (params->cman_params != NULL) {
- s->cman_enabled = true;
status = rte_sched_cman_config(port, s, params, n_subports);
if (status) {
- RTE_LOG(NOTICE, SCHED,
- "%s: CMAN configuration fails\n", __func__);
- return status;
+ if (status != 1) {
+ RTE_LOG(NOTICE, SCHED,
+ "%s: CMAN configuration fails\n", __func__);
+ return status;
+ }
+ } else {
+ s->cman_enabled = true;
}
- } else {
- s->cman_enabled = false;
}
-#endif
/* Scheduling loop detection */
s->pipe_loop = RTE_SCHED_PIPE_INVALID;
@@ -1825,14 +1823,10 @@ rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport *subport,
qe->stats.n_pkts_dropped += 1;
qe->stats.n_bytes_dropped += pkt_len;
-#ifdef RTE_SCHED_CMAN
if (subport->cman_enabled)
qe->stats.n_pkts_cman_dropped += n_pkts_cman_dropped;
-#endif
}
-#ifdef RTE_SCHED_CMAN
-
static inline int
rte_sched_port_cman_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
@@ -1902,29 +1896,6 @@ uint32_t qindex, uint32_t pkt_len, uint64_t time) {
}
}
-#else
-
-static inline int rte_sched_port_cman_drop(struct rte_sched_port *port __rte_unused,
- struct rte_sched_subport *subport __rte_unused,
- struct rte_mbuf *pkt __rte_unused,
- uint32_t qindex __rte_unused,
- uint16_t qlen __rte_unused)
-{
- return 0;
-}
-
-#define rte_sched_port_red_set_queue_empty_timestamp(port, subport, qindex)
-
-static inline void
-rte_sched_port_pie_dequeue(struct rte_sched_subport *subport __rte_unused,
- uint32_t qindex __rte_unused,
- uint32_t pkt_len __rte_unused,
- uint64_t time __rte_unused) {
- /* do-nothing when RTE_SCHED_CMAN not defined */
-}
-
-#endif /* RTE_SCHED_CMAN */
-
#ifdef RTE_SCHED_DEBUG
static inline void
diff --git a/lib/sched/rte_sched.h b/lib/sched/rte_sched.h
index 5ece64e527..ce03fadf5c 100644
--- a/lib/sched/rte_sched.h
+++ b/lib/sched/rte_sched.h
@@ -126,6 +126,7 @@ extern "C" {
* information, refer RFC8033.
*/
enum rte_sched_cman_mode {
+ RTE_SCHED_CMAN_NONE, /**< no RED|PIE cfg available */
RTE_SCHED_CMAN_RED, /**< Random Early Detection (RED) */
RTE_SCHED_CMAN_PIE, /**< Proportional Integral Controller Enhanced (PIE) */
};
--
2.25.1
--------------------------------------------------------------
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2] sched: enable CMAN at runtime
2022-05-11 13:53 [PATCH] sched: enable CMAN at runtime Marcin Danilewicz
@ 2022-05-12 13:10 ` Marcin Danilewicz
2022-05-30 11:19 ` Dumitrescu, Cristian
` (2 more replies)
0 siblings, 3 replies; 27+ messages in thread
From: Marcin Danilewicz @ 2022-05-12 13:10 UTC (permalink / raw)
To: dev, jasvinder.singh, cristian.dumitrescu; +Cc: megha.ajmera
Added changes to enable CMAN (RED or PIE) at init
from profile configuration file.
By default CMAN code is enable but not in use, when
there is no RED or PIE profile configured.
Log: v2 change in rte_sched.h to avoid ABI breakage.
Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
---
config/rte_config.h | 3 -
drivers/net/softnic/rte_eth_softnic_tm.c | 12 --
examples/ip_pipeline/tmgr.c | 4 -
examples/qos_sched/cfg_file.c | 14 +--
examples/qos_sched/cfg_file.h | 2 -
examples/qos_sched/init.c | 4 -
examples/qos_sched/main.h | 2 -
examples/qos_sched/profile.cfg | 130 ++++++++++-----------
examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++
examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++
lib/sched/rte_sched.c | 53 ++-------
lib/sched/rte_sched.h | 2 +
12 files changed, 371 insertions(+), 140 deletions(-)
create mode 100644 examples/qos_sched/profile_pie.cfg
create mode 100644 examples/qos_sched/profile_red.cfg
diff --git a/config/rte_config.h b/config/rte_config.h
index 8eb29c1525..1740a1d053 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -88,9 +88,6 @@
/* rte_power defines */
#define RTE_MAX_LCORE_FREQS 64
-/* rte_sched defines */
-#undef RTE_SCHED_CMAN
-
/* rte_graph defines */
#define RTE_GRAPH_BURST_SIZE 256
#define RTE_LIBRTE_GRAPH_STATS 1
diff --git a/drivers/net/softnic/rte_eth_softnic_tm.c b/drivers/net/softnic/rte_eth_softnic_tm.c
index 6a7766ba1c..3a5fd676e9 100644
--- a/drivers/net/softnic/rte_eth_softnic_tm.c
+++ b/drivers/net/softnic/rte_eth_softnic_tm.c
@@ -420,11 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,
return 0;
}
-#ifdef RTE_SCHED_CMAN
#define WRED_SUPPORTED 1
-#else
-#define WRED_SUPPORTED 0
-#endif
#define STATS_MASK_DEFAULT \
(RTE_TM_STATS_N_PKTS | \
@@ -2300,8 +2296,6 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev, uint32_t tc_id)
return NULL;
}
-#ifdef RTE_SCHED_CMAN
-
static void
wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
{
@@ -2325,12 +2319,6 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
}
}
-#else
-
-#define wred_profiles_set(dev, subport_id)
-
-#endif
-
static struct tm_shared_shaper *
tm_tc_shared_shaper_get(struct rte_eth_dev *dev, struct tm_node *tc_node)
{
diff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c
index b138e885cf..e68e9961be 100644
--- a/examples/ip_pipeline/tmgr.c
+++ b/examples/ip_pipeline/tmgr.c
@@ -17,7 +17,6 @@ static uint32_t n_subport_profiles;
static struct rte_sched_pipe_params
pipe_profile[TMGR_PIPE_PROFILE_MAX];
-#ifdef RTE_SCHED_CMAN
static struct rte_sched_cman_params cman_params = {
.red_params = {
/* Traffic Class 0 Colors Green / Yellow / Red */
@@ -86,7 +85,6 @@ static struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
static uint32_t n_pipe_profiles;
@@ -96,9 +94,7 @@ static const struct rte_sched_subport_params subport_params_default = {
.pipe_profiles = pipe_profile,
.n_pipe_profiles = 0, /* filled at run time */
.n_max_pipe_profiles = RTE_DIM(pipe_profile),
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
};
static struct tmgr_port_list tmgr_port_list;
diff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c
index 450482f07d..efff1dbb01 100644
--- a/examples/qos_sched/cfg_file.c
+++ b/examples/qos_sched/cfg_file.c
@@ -229,13 +229,15 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg,
return 0;
}
-#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p)
{
int j, k;
subport_p->cman_params->cman_mode = cman_p.cman_mode;
+ if (subport_p->cman_params->cman_mode == RTE_SCHED_CMAN_NONE)
+ return;
+
for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
if (subport_p->cman_params->cman_mode ==
RTE_SCHED_CMAN_RED) {
@@ -261,7 +263,6 @@ void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
}
}
}
-#endif
int
cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)
@@ -276,12 +277,14 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
memset(active_queues, 0, sizeof(active_queues));
n_active_queues = 0;
-#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
- .cman_mode = RTE_SCHED_CMAN_RED,
.red_params = { },
};
+ if (cman_params.cman_mode != RTE_SCHED_CMAN_NONE) {
+ cman_params.cman_mode = RTE_SCHED_CMAN_NONE;
+ }
+
if (rte_cfgfile_has_section(cfg, "red")) {
cman_params.cman_mode = RTE_SCHED_CMAN_RED;
@@ -387,7 +390,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
-#endif /* RTE_SCHED_CMAN */
for (i = 0; i < MAX_SCHED_SUBPORTS; i++) {
char sec_name[CFG_NAME_LEN];
@@ -465,9 +467,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
}
-#ifdef RTE_SCHED_CMAN
set_subport_cman_params(subport_params+i, cman_params);
-#endif
}
}
diff --git a/examples/qos_sched/cfg_file.h b/examples/qos_sched/cfg_file.h
index 1a9dce9db5..19df91e7ba 100644
--- a/examples/qos_sched/cfg_file.h
+++ b/examples/qos_sched/cfg_file.h
@@ -12,10 +12,8 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);
int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);
-#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p);
-#endif
int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);
diff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c
index 8a0fb8a374..0afd553283 100644
--- a/examples/qos_sched/init.c
+++ b/examples/qos_sched/init.c
@@ -201,7 +201,6 @@ static struct rte_sched_subport_profile_params
},
};
-#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
.cman_mode = RTE_SCHED_CMAN_RED,
.red_params = {
@@ -271,7 +270,6 @@ struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
{
@@ -281,9 +279,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
.n_pipe_profiles = sizeof(pipe_profiles) /
sizeof(struct rte_sched_pipe_params),
.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
},
};
diff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h
index 915311bac8..76a68f585f 100644
--- a/examples/qos_sched/main.h
+++ b/examples/qos_sched/main.h
@@ -153,9 +153,7 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
extern uint32_t n_active_queues;
extern struct rte_sched_port_params port_params;
-#ifdef RTE_SCHED_CMAN
extern struct rte_sched_cman_params cman_params;
-#endif
extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];
int app_parse_args(int argc, char **argv);
diff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg
index d4b21c0170..db65b0ed01 100644
--- a/examples/qos_sched/profile.cfg
+++ b/examples/qos_sched/profile.cfg
@@ -142,68 +142,68 @@ tc 12 wrr weights = 1 1 1 1
;tc 12 wred inv prob = 10 10 10
;tc 12 wred weight = 9 9 9
-[pie]
-tc 0 qdelay ref = 15
-tc 0 max burst = 150
-tc 0 update interval = 15
-tc 0 tailq th = 64
-
-tc 1 qdelay ref = 15
-tc 1 max burst = 150
-tc 1 update interval = 15
-tc 1 tailq th = 64
-
-tc 2 qdelay ref = 15
-tc 2 max burst = 150
-tc 2 update interval = 15
-tc 2 tailq th = 64
-
-tc 3 qdelay ref = 15
-tc 3 max burst = 150
-tc 3 update interval = 15
-tc 3 tailq th = 64
-
-tc 4 qdelay ref = 15
-tc 4 max burst = 150
-tc 4 update interval = 15
-tc 4 tailq th = 64
-
-tc 5 qdelay ref = 15
-tc 5 max burst = 150
-tc 5 update interval = 15
-tc 5 tailq th = 64
-
-tc 6 qdelay ref = 15
-tc 6 max burst = 150
-tc 6 update interval = 15
-tc 6 tailq th = 64
-
-tc 7 qdelay ref = 15
-tc 7 max burst = 150
-tc 7 update interval = 15
-tc 7 tailq th = 64
-
-tc 8 qdelay ref = 15
-tc 8 max burst = 150
-tc 8 update interval = 15
-tc 8 tailq th = 64
-
-tc 9 qdelay ref = 15
-tc 9 max burst = 150
-tc 9 update interval = 15
-tc 9 tailq th = 64
-
-tc 10 qdelay ref = 15
-tc 10 max burst = 150
-tc 10 update interval = 15
-tc 10 tailq th = 64
-
-tc 11 qdelay ref = 15
-tc 11 max burst = 150
-tc 11 update interval = 15
-tc 11 tailq th = 64
-
-tc 12 qdelay ref = 15
-tc 12 max burst = 150
-tc 12 update interval = 15
-tc 12 tailq th = 64
+;[pie]
+;tc 0 qdelay ref = 15
+;tc 0 max burst = 150
+;tc 0 update interval = 15
+;tc 0 tailq th = 64
+
+;tc 1 qdelay ref = 15
+;tc 1 max burst = 150
+;tc 1 update interval = 15
+;tc 1 tailq th = 64
+
+;tc 2 qdelay ref = 15
+;tc 2 max burst = 150
+;tc 2 update interval = 15
+;tc 2 tailq th = 64
+
+;tc 3 qdelay ref = 15
+;tc 3 max burst = 150
+;tc 3 update interval = 15
+;tc 3 tailq th = 64
+
+;tc 4 qdelay ref = 15
+;tc 4 max burst = 150
+;tc 4 update interval = 15
+;tc 4 tailq th = 64
+
+;tc 5 qdelay ref = 15
+;tc 5 max burst = 150
+;tc 5 update interval = 15
+;tc 5 tailq th = 64
+
+;tc 6 qdelay ref = 15
+;tc 6 max burst = 150
+;tc 6 update interval = 15
+;tc 6 tailq th = 64
+
+;tc 7 qdelay ref = 15
+;tc 7 max burst = 150
+;tc 7 update interval = 15
+;tc 7 tailq th = 64
+
+;tc 8 qdelay ref = 15
+;tc 8 max burst = 150
+;tc 8 update interval = 15
+;tc 8 tailq th = 64
+
+;tc 9 qdelay ref = 15
+;tc 9 max burst = 150
+;tc 9 update interval = 15
+;tc 9 tailq th = 64
+
+;tc 10 qdelay ref = 15
+;tc 10 max burst = 150
+;tc 10 update interval = 15
+;tc 10 tailq th = 64
+
+;tc 11 qdelay ref = 15
+;tc 11 max burst = 150
+;tc 11 update interval = 15
+;tc 11 tailq th = 64
+
+;tc 12 qdelay ref = 15
+;tc 12 max burst = 150
+;tc 12 update interval = 15
+;tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_pie.cfg b/examples/qos_sched/profile_pie.cfg
new file mode 100644
index 0000000000..241f748b33
--- /dev/null
+++ b/examples/qos_sched/profile_pie.cfg
@@ -0,0 +1,142 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+[pie]
+tc 0 qdelay ref = 15
+tc 0 max burst = 150
+tc 0 update interval = 15
+tc 0 tailq th = 64
+
+tc 1 qdelay ref = 15
+tc 1 max burst = 150
+tc 1 update interval = 15
+tc 1 tailq th = 64
+
+tc 2 qdelay ref = 15
+tc 2 max burst = 150
+tc 2 update interval = 15
+tc 2 tailq th = 64
+
+tc 3 qdelay ref = 15
+tc 3 max burst = 150
+tc 3 update interval = 15
+tc 3 tailq th = 64
+
+tc 4 qdelay ref = 15
+tc 4 max burst = 150
+tc 4 update interval = 15
+tc 4 tailq th = 64
+
+tc 5 qdelay ref = 15
+tc 5 max burst = 150
+tc 5 update interval = 15
+tc 5 tailq th = 64
+
+tc 6 qdelay ref = 15
+tc 6 max burst = 150
+tc 6 update interval = 15
+tc 6 tailq th = 64
+
+tc 7 qdelay ref = 15
+tc 7 max burst = 150
+tc 7 update interval = 15
+tc 7 tailq th = 64
+
+tc 8 qdelay ref = 15
+tc 8 max burst = 150
+tc 8 update interval = 15
+tc 8 tailq th = 64
+
+tc 9 qdelay ref = 15
+tc 9 max burst = 150
+tc 9 update interval = 15
+tc 9 tailq th = 64
+
+tc 10 qdelay ref = 15
+tc 10 max burst = 150
+tc 10 update interval = 15
+tc 10 tailq th = 64
+
+tc 11 qdelay ref = 15
+tc 11 max burst = 150
+tc 11 update interval = 15
+tc 11 tailq th = 64
+
+tc 12 qdelay ref = 15
+tc 12 max burst = 150
+tc 12 update interval = 15
+tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_red.cfg b/examples/qos_sched/profile_red.cfg
new file mode 100644
index 0000000000..4486d2799e
--- /dev/null
+++ b/examples/qos_sched/profile_red.cfg
@@ -0,0 +1,143 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+; RED params per traffic class and color (Green / Yellow / Red)
+[red]
+tc 0 wred min = 48 40 32
+tc 0 wred max = 64 64 64
+tc 0 wred inv prob = 10 10 10
+tc 0 wred weight = 9 9 9
+
+tc 1 wred min = 48 40 32
+tc 1 wred max = 64 64 64
+tc 1 wred inv prob = 10 10 10
+tc 1 wred weight = 9 9 9
+
+tc 2 wred min = 48 40 32
+tc 2 wred max = 64 64 64
+tc 2 wred inv prob = 10 10 10
+tc 2 wred weight = 9 9 9
+
+tc 3 wred min = 48 40 32
+tc 3 wred max = 64 64 64
+tc 3 wred inv prob = 10 10 10
+tc 3 wred weight = 9 9 9
+
+tc 4 wred min = 48 40 32
+tc 4 wred max = 64 64 64
+tc 4 wred inv prob = 10 10 10
+tc 4 wred weight = 9 9 9
+
+tc 5 wred min = 48 40 32
+tc 5 wred max = 64 64 64
+tc 5 wred inv prob = 10 10 10
+tc 5 wred weight = 9 9 9
+
+tc 6 wred min = 48 40 32
+tc 6 wred max = 64 64 64
+tc 6 wred inv prob = 10 10 10
+tc 6 wred weight = 9 9 9
+
+tc 7 wred min = 48 40 32
+tc 7 wred max = 64 64 64
+tc 7 wred inv prob = 10 10 10
+tc 7 wred weight = 9 9 9
+
+tc 8 wred min = 48 40 32
+tc 8 wred max = 64 64 64
+tc 8 wred inv prob = 10 10 10
+tc 8 wred weight = 9 9 9
+
+tc 9 wred min = 48 40 32
+tc 9 wred max = 64 64 64
+tc 9 wred inv prob = 10 10 10
+tc 9 wred weight = 9 9 9
+
+tc 10 wred min = 48 40 32
+tc 10 wred max = 64 64 64
+tc 10 wred inv prob = 10 10 10
+tc 10 wred weight = 9 9 9
+
+tc 11 wred min = 48 40 32
+tc 11 wred max = 64 64 64
+tc 11 wred inv prob = 10 10 10
+tc 11 wred weight = 9 9 9
+
+tc 12 wred min = 48 40 32
+tc 12 wred max = 64 64 64
+tc 12 wred inv prob = 10 10 10
+tc 12 wred weight = 9 9 9
diff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c
index ec74bee939..db14934832 100644
--- a/lib/sched/rte_sched.c
+++ b/lib/sched/rte_sched.c
@@ -81,13 +81,11 @@ struct rte_sched_queue {
struct rte_sched_queue_extra {
struct rte_sched_queue_stats stats;
-#ifdef RTE_SCHED_CMAN
RTE_STD_C11
union {
struct rte_red red;
struct rte_pie pie;
};
-#endif
};
enum grinder_state {
@@ -179,7 +177,6 @@ struct rte_sched_subport {
/* Pipe queues size */
uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
-#ifdef RTE_SCHED_CMAN
bool cman_enabled;
enum rte_sched_cman_mode cman;
@@ -188,7 +185,6 @@ struct rte_sched_subport {
struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];
struct rte_pie_config pie_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
};
-#endif
/* Scheduling loop detection */
uint32_t pipe_loop;
@@ -1081,7 +1077,6 @@ rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports)
rte_free(port);
}
-#ifdef RTE_SCHED_CMAN
static int
rte_sched_red_config(struct rte_sched_port *port,
struct rte_sched_subport *s,
@@ -1161,9 +1156,11 @@ rte_sched_cman_config(struct rte_sched_port *port,
else if (params->cman_params->cman_mode == RTE_SCHED_CMAN_PIE)
return rte_sched_pie_config(port, s, params, n_subports);
+ else if (params->cman_params->cman_mode == RTE_SCHED_CMAN_NONE)
+ return 1;
+
return -EINVAL;
}
-#endif
int
rte_sched_subport_config(struct rte_sched_port *port,
@@ -1254,19 +1251,20 @@ rte_sched_subport_config(struct rte_sched_port *port,
s->n_pipe_profiles = params->n_pipe_profiles;
s->n_max_pipe_profiles = params->n_max_pipe_profiles;
-#ifdef RTE_SCHED_CMAN
+ s->cman_enabled = false;
+
if (params->cman_params != NULL) {
- s->cman_enabled = true;
status = rte_sched_cman_config(port, s, params, n_subports);
if (status) {
- RTE_LOG(NOTICE, SCHED,
- "%s: CMAN configuration fails\n", __func__);
- return status;
+ if (status != 1) {
+ RTE_LOG(NOTICE, SCHED,
+ "%s: CMAN configuration fails\n", __func__);
+ return status;
+ }
+ } else {
+ s->cman_enabled = true;
}
- } else {
- s->cman_enabled = false;
}
-#endif
/* Scheduling loop detection */
s->pipe_loop = RTE_SCHED_PIPE_INVALID;
@@ -1825,14 +1823,10 @@ rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport *subport,
qe->stats.n_pkts_dropped += 1;
qe->stats.n_bytes_dropped += pkt_len;
-#ifdef RTE_SCHED_CMAN
if (subport->cman_enabled)
qe->stats.n_pkts_cman_dropped += n_pkts_cman_dropped;
-#endif
}
-#ifdef RTE_SCHED_CMAN
-
static inline int
rte_sched_port_cman_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
@@ -1902,29 +1896,6 @@ uint32_t qindex, uint32_t pkt_len, uint64_t time) {
}
}
-#else
-
-static inline int rte_sched_port_cman_drop(struct rte_sched_port *port __rte_unused,
- struct rte_sched_subport *subport __rte_unused,
- struct rte_mbuf *pkt __rte_unused,
- uint32_t qindex __rte_unused,
- uint16_t qlen __rte_unused)
-{
- return 0;
-}
-
-#define rte_sched_port_red_set_queue_empty_timestamp(port, subport, qindex)
-
-static inline void
-rte_sched_port_pie_dequeue(struct rte_sched_subport *subport __rte_unused,
- uint32_t qindex __rte_unused,
- uint32_t pkt_len __rte_unused,
- uint64_t time __rte_unused) {
- /* do-nothing when RTE_SCHED_CMAN not defined */
-}
-
-#endif /* RTE_SCHED_CMAN */
-
#ifdef RTE_SCHED_DEBUG
static inline void
diff --git a/lib/sched/rte_sched.h b/lib/sched/rte_sched.h
index 5ece64e527..82aa73ff5b 100644
--- a/lib/sched/rte_sched.h
+++ b/lib/sched/rte_sched.h
@@ -128,6 +128,8 @@ extern "C" {
enum rte_sched_cman_mode {
RTE_SCHED_CMAN_RED, /**< Random Early Detection (RED) */
RTE_SCHED_CMAN_PIE, /**< Proportional Integral Controller Enhanced (PIE) */
+ /* New enum RTE_SCHED_CMAN_NONE added at the end to avoid ABI breakage */
+ RTE_SCHED_CMAN_NONE, /**< no RED|PIE cfg available */
};
/*
--
2.25.1
--------------------------------------------------------------
Intel Research and Development Ireland Limited
Registered in Ireland
Registered Office: Collinstown Industrial Park, Leixlip, County Kildare
Registered Number: 308263
This e-mail and any attachments may contain confidential material for the sole
use of the intended recipient(s). Any review or distribution by others is
strictly prohibited. If you are not the intended recipient, please contact the
sender and delete all copies.
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v2] sched: enable CMAN at runtime
2022-05-12 13:10 ` [PATCH v2] " Marcin Danilewicz
@ 2022-05-30 11:19 ` Dumitrescu, Cristian
2022-05-30 14:03 ` Danilewicz, MarcinX
2022-06-02 9:57 ` Danilewicz, MarcinX
2022-05-30 11:35 ` Dumitrescu, Cristian
2022-06-08 9:42 ` [PATCH v3] " Marcin Danilewicz
2 siblings, 2 replies; 27+ messages in thread
From: Dumitrescu, Cristian @ 2022-05-30 11:19 UTC (permalink / raw)
To: Danilewicz, MarcinX, dev, Singh, Jasvinder; +Cc: Ajmera, Megha
> -----Original Message-----
> From: Danilewicz, MarcinX <marcinx.danilewicz@intel.com>
> Sent: Thursday, May 12, 2022 2:11 PM
> To: dev@dpdk.org; Singh, Jasvinder <jasvinder.singh@intel.com>;
> Dumitrescu, Cristian <cristian.dumitrescu@intel.com>
> Cc: Ajmera, Megha <megha.ajmera@intel.com>
> Subject: [PATCH v2] sched: enable CMAN at runtime
>
> Added changes to enable CMAN (RED or PIE) at init
> from profile configuration file.
>
> By default CMAN code is enable but not in use, when
> there is no RED or PIE profile configured.
>
> Log: v2 change in rte_sched.h to avoid ABI breakage.
>
> Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
> ---
> config/rte_config.h | 3 -
> drivers/net/softnic/rte_eth_softnic_tm.c | 12 --
> examples/ip_pipeline/tmgr.c | 4 -
> examples/qos_sched/cfg_file.c | 14 +--
> examples/qos_sched/cfg_file.h | 2 -
> examples/qos_sched/init.c | 4 -
> examples/qos_sched/main.h | 2 -
> examples/qos_sched/profile.cfg | 130 ++++++++++-----------
> examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++
> examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++
> lib/sched/rte_sched.c | 53 ++-------
> lib/sched/rte_sched.h | 2 +
> 12 files changed, 371 insertions(+), 140 deletions(-)
> create mode 100644 examples/qos_sched/profile_pie.cfg
> create mode 100644 examples/qos_sched/profile_red.cfg
>
> diff --git a/lib/sched/rte_sched.h b/lib/sched/rte_sched.h
> index 5ece64e527..82aa73ff5b 100644
> --- a/lib/sched/rte_sched.h
> +++ b/lib/sched/rte_sched.h
> @@ -128,6 +128,8 @@ extern "C" {
> enum rte_sched_cman_mode {
> RTE_SCHED_CMAN_RED, /**< Random Early Detection (RED) */
> RTE_SCHED_CMAN_PIE, /**< Proportional Integral Controller
> Enhanced (PIE) */
> + /* New enum RTE_SCHED_CMAN_NONE added at the end to avoid
> ABI breakage */
> + RTE_SCHED_CMAN_NONE, /**< no RED|PIE cfg available */
> };
Can you please explain why you need to add the new RTE_SCHED_CMAN_NONE value to this enumeration and what is the ABI breakage that you are trying to avoid?
The library expects the struct rte_sched_subport_params:: cman_params to be NULL when the CMAN is disabled, why is this not enough to detect that CMAN is disabled? I suggest to keep the current approach.
>
> /*
> --
> 2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v2] sched: enable CMAN at runtime
2022-05-12 13:10 ` [PATCH v2] " Marcin Danilewicz
2022-05-30 11:19 ` Dumitrescu, Cristian
@ 2022-05-30 11:35 ` Dumitrescu, Cristian
2022-06-07 10:40 ` Danilewicz, MarcinX
2022-06-08 9:42 ` [PATCH v3] " Marcin Danilewicz
2 siblings, 1 reply; 27+ messages in thread
From: Dumitrescu, Cristian @ 2022-05-30 11:35 UTC (permalink / raw)
To: Danilewicz, MarcinX, dev, Singh, Jasvinder; +Cc: Ajmera, Megha, Liu, Yu Y
Hi Marcin,
Comments inline below.
> -----Original Message-----
> From: Danilewicz, MarcinX <marcinx.danilewicz@intel.com>
> Sent: Thursday, May 12, 2022 2:11 PM
> To: dev@dpdk.org; Singh, Jasvinder <jasvinder.singh@intel.com>;
> Dumitrescu, Cristian <cristian.dumitrescu@intel.com>
> Cc: Ajmera, Megha <megha.ajmera@intel.com>
> Subject: [PATCH v2] sched: enable CMAN at runtime
>
> Added changes to enable CMAN (RED or PIE) at init
> from profile configuration file.
>
> By default CMAN code is enable but not in use, when
> there is no RED or PIE profile configured.
>
> Log: v2 change in rte_sched.h to avoid ABI breakage.
>
> Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
> ---
> config/rte_config.h | 3 -
> drivers/net/softnic/rte_eth_softnic_tm.c | 12 --
> examples/ip_pipeline/tmgr.c | 4 -
> examples/qos_sched/cfg_file.c | 14 +--
> examples/qos_sched/cfg_file.h | 2 -
> examples/qos_sched/init.c | 4 -
> examples/qos_sched/main.h | 2 -
> examples/qos_sched/profile.cfg | 130 ++++++++++-----------
> examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++
> examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++
> lib/sched/rte_sched.c | 53 ++-------
> lib/sched/rte_sched.h | 2 +
> 12 files changed, 371 insertions(+), 140 deletions(-)
> create mode 100644 examples/qos_sched/profile_pie.cfg
> create mode 100644 examples/qos_sched/profile_red.cfg
>
<snip>
> diff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c
> index ec74bee939..db14934832 100644
> --- a/lib/sched/rte_sched.c
> +++ b/lib/sched/rte_sched.c
<snip>
> -#ifdef RTE_SCHED_CMAN
> static int
> rte_sched_red_config(struct rte_sched_port *port,
> struct rte_sched_subport *s,
> @@ -1161,9 +1156,11 @@ rte_sched_cman_config(struct rte_sched_port
> *port,
> else if (params->cman_params->cman_mode ==
> RTE_SCHED_CMAN_PIE)
> return rte_sched_pie_config(port, s, params, n_subports);
>
> + else if (params->cman_params->cman_mode ==
> RTE_SCHED_CMAN_NONE)
> + return 1;
> +
> return -EINVAL;
> }
> -#endif
Yes, you do need to remove the #ifdef ... #endif around this function, but no, you don't need to change this function, as it is only called when params->cman_params != NULL, i.e. CMAN is enabled. As mentioned before, there is no need to add the CMAN_NONE to the enumeration, as the CMAN_NONE value is equivalent to params->cman_params being set to NULL.
>
> int
> rte_sched_subport_config(struct rte_sched_port *port,
> @@ -1254,19 +1251,20 @@ rte_sched_subport_config(struct
> rte_sched_port *port,
> s->n_pipe_profiles = params->n_pipe_profiles;
> s->n_max_pipe_profiles = params->n_max_pipe_profiles;
>
> -#ifdef RTE_SCHED_CMAN
> + s->cman_enabled = false;
> +
> if (params->cman_params != NULL) {
> - s->cman_enabled = true;
> status = rte_sched_cman_config(port, s, params,
> n_subports);
> if (status) {
> - RTE_LOG(NOTICE, SCHED,
> - "%s: CMAN configuration fails\n",
> __func__);
> - return status;
> + if (status != 1) {
> + RTE_LOG(NOTICE, SCHED,
> + "%s: CMAN configuration
> fails\n", __func__);
> + return status;
> + }
> + } else {
> + s->cman_enabled = true;
> }
> - } else {
> - s->cman_enabled = false;
> }
> -#endif
>
Same comment here: yes, remove the #ifdef ... #endif, but no need to change this code fragment, as it sets correctly the s->cman_enabled flag, which is then the only flag used by the rest of the code. Again, no need to have a CMAN_NONE in the enumeration, as the same is achieved by setting params->cman_params to NULL.
> /* Scheduling loop detection */
> s->pipe_loop = RTE_SCHED_PIPE_INVALID;
> @@ -1825,14 +1823,10 @@
> rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport
> *subport,
>
> qe->stats.n_pkts_dropped += 1;
> qe->stats.n_bytes_dropped += pkt_len;
> -#ifdef RTE_SCHED_CMAN
> if (subport->cman_enabled)
> qe->stats.n_pkts_cman_dropped += n_pkts_cman_dropped;
> -#endif
> }
Please don't forget to remove the __rte_unused attribute for the n_pkts_cman_dropped in the function parameters, right?
<snip>
Regards,
Cristian
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v2] sched: enable CMAN at runtime
2022-05-30 11:19 ` Dumitrescu, Cristian
@ 2022-05-30 14:03 ` Danilewicz, MarcinX
2022-06-02 9:57 ` Danilewicz, MarcinX
1 sibling, 0 replies; 27+ messages in thread
From: Danilewicz, MarcinX @ 2022-05-30 14:03 UTC (permalink / raw)
To: Dumitrescu, Cristian, dev, Singh, Jasvinder; +Cc: Ajmera, Megha
Hi Cristian,
> Can you please explain why you need to add the new
> RTE_SCHED_CMAN_NONE value to this enumeration and what is the ABI
> breakage that you are trying to avoid?
>
> The library expects the struct rte_sched_subport_params:: cman_params to
> be NULL when the CMAN is disabled, why is this not enough to detect that
> CMAN is disabled? I suggest to keep the current approach.
Well, that above was just another approach. I'll have look to follow your advice, because there should be a third case when no RED or PIR config was found in files.
So I used third enum to detect this case, like here:
> + else if (params->cman_params->cman_mode ==
> RTE_SCHED_CMAN_NONE)
> + return 1;
Also I got this advice to move RTE_SCHED_CMAN_NONE to the bottom to remove ABI warnings, because structure in header file has changed without change in map files (?) for that?
Here is some more detailed log with errors:
1 data member change:
type of 'rte_sched_cman_params* rte_sched_subport_params::cman_params' changed:
in pointed to type 'struct rte_sched_cman_params' at rte_sched.h:166:1:
type size hasn't changed
1 data member change:
type of 'rte_sched_cman_mode rte_sched_cman_params::cman_mode' changed:
type size hasn't changed
1 enumerator insertion:
'rte_sched_cman_mode::RTE_SCHED_CMAN_NONE' value '0'
2 enumerator changes:
'rte_sched_cman_mode::RTE_SCHED_CMAN_RED' from value '0' to '1' at rte_sched.h:128:1
'rte_sched_cman_mode::RTE_SCHED_CMAN_PIE' from value '1' to '2' at rte_sched.h:128:1
Error: ABI issue reported for 'abidiff --suppr devtools/libabigail.abignore --no-added-syms --headers-dir1 reference/usr/local/include --headers-dir2 install/usr/local/include reference/dump/librte_sched.dump install/dump/librte_sched.dump'
ABIDIFF_ABI_CHANGE, this change requires a review (abidiff flagged this as a potential issue).
Kind Regards,
/Marcin
--------------------------------------------------------------
Intel Research and Development Ireland Limited
Registered in Ireland
Registered Office: Collinstown Industrial Park, Leixlip, County Kildare
Registered Number: 308263
This e-mail and any attachments may contain confidential material for the sole
use of the intended recipient(s). Any review or distribution by others is
strictly prohibited. If you are not the intended recipient, please contact the
sender and delete all copies.
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v2] sched: enable CMAN at runtime
2022-05-30 11:19 ` Dumitrescu, Cristian
2022-05-30 14:03 ` Danilewicz, MarcinX
@ 2022-06-02 9:57 ` Danilewicz, MarcinX
1 sibling, 0 replies; 27+ messages in thread
From: Danilewicz, MarcinX @ 2022-06-02 9:57 UTC (permalink / raw)
To: Dumitrescu, Cristian, dev, Singh, Jasvinder; +Cc: Ajmera, Megha
+this time to dpdk.org , to test removal of automatic footer
Hi Cristian,
< snip >
> > +++ b/lib/sched/rte_sched.h
> > @@ -128,6 +128,8 @@ extern "C" {
> > enum rte_sched_cman_mode {
> > RTE_SCHED_CMAN_RED, /**< Random Early Detection (RED) */
> > RTE_SCHED_CMAN_PIE, /**< Proportional Integral Controller
< snip >
> Can you please explain why you need to add the new
> RTE_SCHED_CMAN_NONE value to this enumeration and what is the ABI
> breakage that you are trying to avoid?
>
well, it was third value for cases when no RED or PIE is configured from config file
Initially I have found this error:
1 data member change:
type of 'rte_sched_cman_params* rte_sched_subport_params::cman_params' changed:
in pointed to type 'struct rte_sched_cman_params' at rte_sched.h:166:1:
type size hasn't changed
1 data member change:
type of 'rte_sched_cman_mode rte_sched_cman_params::cman_mode' changed:
type size hasn't changed
1 enumerator insertion:
'rte_sched_cman_mode::RTE_SCHED_CMAN_NONE' value '0'
2 enumerator changes:
'rte_sched_cman_mode::RTE_SCHED_CMAN_RED' from value '0' to '1' at rte_sched.h:128:1
'rte_sched_cman_mode::RTE_SCHED_CMAN_PIE' from value '1' to '2' at rte_sched.h:128:1
Error: ABI issue reported for 'abidiff --suppr devtools/libabigail.abignore --no-added-syms
--headers-dir1 reference/usr/local/include --headers-dir2 install/usr/local/include reference
/dump/librte_sched.dump install/dump/librte_sched.dump'
ABIDIFF_ABI_CHANGE, this change requires a review (abidiff flagged this as a potential issue).
Then I moved RTE_SCHED_CMAN_NONE to the end of existing enum, as advices. That removed error above.
In that moment, I needed quick fix for discussion about change for showing approach. Not final fix.
< snip >
> The library expects the struct rte_sched_subport_params:: cman_params to
> be NULL when the CMAN is disabled, why is this not enough to detect that
> CMAN is disabled? I suggest to keep the current approach.
Ok, I'll try to use NULL instead.
Kind Regards,
/Marcin
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v2] sched: enable CMAN at runtime
2022-05-30 11:35 ` Dumitrescu, Cristian
@ 2022-06-07 10:40 ` Danilewicz, MarcinX
0 siblings, 0 replies; 27+ messages in thread
From: Danilewicz, MarcinX @ 2022-06-07 10:40 UTC (permalink / raw)
To: Dumitrescu, Cristian, dev, Singh, Jasvinder; +Cc: Ajmera, Megha, Liu, Yu Y
Hi Cristian,
Please find answers inline.
<snip>
> > Log: v2 change in rte_sched.h to avoid ABI breakage.
<snip>
Lessons learned, so I have fixed also positioning of this above.
<snip>
> > diff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c index
> > ec74bee939..db14934832 100644
> > --- a/lib/sched/rte_sched.c
> > +++ b/lib/sched/rte_sched.c
>
<snip>
> Same comment here: yes, remove the #ifdef ... #endif, but no need to
> change this code fragment, as it sets correctly the s->cman_enabled flag,
> which is then the only flag used by the rest of the code. Again, no need to
> have a CMAN_NONE in the enumeration, as the same is achieved by setting
> params->cman_params to NULL.
Yes, with that approach this is better.
<snip>
> > qe->stats.n_pkts_dropped += 1;
> > qe->stats.n_bytes_dropped += pkt_len; -#ifdef RTE_SCHED_CMAN
> > if (subport->cman_enabled)
> > qe->stats.n_pkts_cman_dropped += n_pkts_cman_dropped;
> -#endif }
>
> Please don't forget to remove the __rte_unused attribute for the
> n_pkts_cman_dropped in the function parameters, right?
Nice spot. Looks like this was there for some time.
Regards,
Marcin
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3] sched: enable CMAN at runtime
2022-05-12 13:10 ` [PATCH v2] " Marcin Danilewicz
2022-05-30 11:19 ` Dumitrescu, Cristian
2022-05-30 11:35 ` Dumitrescu, Cristian
@ 2022-06-08 9:42 ` Marcin Danilewicz
2022-06-08 11:59 ` Dumitrescu, Cristian
2022-06-13 9:09 ` [PATCH v4] " Marcin Danilewicz
2 siblings, 2 replies; 27+ messages in thread
From: Marcin Danilewicz @ 2022-06-08 9:42 UTC (permalink / raw)
To: dev, jasvinder.singh, cristian.dumitrescu; +Cc: megha.ajmera
Added changes to enable CMAN (RED or PIE) at init
from profile configuration file.
By default CMAN code is enable but not in use, when
there is no RED or PIE profile configured.
Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
---
Log: v2 change in rte_sched.h to avoid ABI breakage.
v3 changes from comments
---
config/rte_config.h | 3 -
drivers/net/softnic/rte_eth_softnic_tm.c | 12 --
examples/ip_pipeline/tmgr.c | 4 -
examples/qos_sched/cfg_file.c | 11 +-
examples/qos_sched/cfg_file.h | 2 -
examples/qos_sched/init.c | 4 -
examples/qos_sched/main.h | 2 -
examples/qos_sched/profile.cfg | 130 ++++++++++-----------
examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++
examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++
lib/sched/rte_sched.c | 47 +-------
11 files changed, 359 insertions(+), 141 deletions(-)
create mode 100644 examples/qos_sched/profile_pie.cfg
create mode 100644 examples/qos_sched/profile_red.cfg
diff --git a/config/rte_config.h b/config/rte_config.h
index 8eb29c1525..1740a1d053 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -88,9 +88,6 @@
/* rte_power defines */
#define RTE_MAX_LCORE_FREQS 64
-/* rte_sched defines */
-#undef RTE_SCHED_CMAN
-
/* rte_graph defines */
#define RTE_GRAPH_BURST_SIZE 256
#define RTE_LIBRTE_GRAPH_STATS 1
diff --git a/drivers/net/softnic/rte_eth_softnic_tm.c b/drivers/net/softnic/rte_eth_softnic_tm.c
index 6a7766ba1c..3a5fd676e9 100644
--- a/drivers/net/softnic/rte_eth_softnic_tm.c
+++ b/drivers/net/softnic/rte_eth_softnic_tm.c
@@ -420,11 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,
return 0;
}
-#ifdef RTE_SCHED_CMAN
#define WRED_SUPPORTED 1
-#else
-#define WRED_SUPPORTED 0
-#endif
#define STATS_MASK_DEFAULT \
(RTE_TM_STATS_N_PKTS | \
@@ -2300,8 +2296,6 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev, uint32_t tc_id)
return NULL;
}
-#ifdef RTE_SCHED_CMAN
-
static void
wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
{
@@ -2325,12 +2319,6 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
}
}
-#else
-
-#define wred_profiles_set(dev, subport_id)
-
-#endif
-
static struct tm_shared_shaper *
tm_tc_shared_shaper_get(struct rte_eth_dev *dev, struct tm_node *tc_node)
{
diff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c
index b138e885cf..e68e9961be 100644
--- a/examples/ip_pipeline/tmgr.c
+++ b/examples/ip_pipeline/tmgr.c
@@ -17,7 +17,6 @@ static uint32_t n_subport_profiles;
static struct rte_sched_pipe_params
pipe_profile[TMGR_PIPE_PROFILE_MAX];
-#ifdef RTE_SCHED_CMAN
static struct rte_sched_cman_params cman_params = {
.red_params = {
/* Traffic Class 0 Colors Green / Yellow / Red */
@@ -86,7 +85,6 @@ static struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
static uint32_t n_pipe_profiles;
@@ -96,9 +94,7 @@ static const struct rte_sched_subport_params subport_params_default = {
.pipe_profiles = pipe_profile,
.n_pipe_profiles = 0, /* filled at run time */
.n_max_pipe_profiles = RTE_DIM(pipe_profile),
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
};
static struct tmgr_port_list tmgr_port_list;
diff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c
index 450482f07d..3284b4d252 100644
--- a/examples/qos_sched/cfg_file.c
+++ b/examples/qos_sched/cfg_file.c
@@ -229,11 +229,14 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg,
return 0;
}
-#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p)
{
int j, k;
+
+ if (subport_p->cman_params != NULL)
+ return;
+
subport_p->cman_params->cman_mode = cman_p.cman_mode;
for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
@@ -261,7 +264,6 @@ void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
}
}
}
-#endif
int
cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)
@@ -276,9 +278,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
memset(active_queues, 0, sizeof(active_queues));
n_active_queues = 0;
-#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
- .cman_mode = RTE_SCHED_CMAN_RED,
.red_params = { },
};
@@ -387,7 +387,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
-#endif /* RTE_SCHED_CMAN */
for (i = 0; i < MAX_SCHED_SUBPORTS; i++) {
char sec_name[CFG_NAME_LEN];
@@ -465,9 +464,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
}
-#ifdef RTE_SCHED_CMAN
set_subport_cman_params(subport_params+i, cman_params);
-#endif
}
}
diff --git a/examples/qos_sched/cfg_file.h b/examples/qos_sched/cfg_file.h
index 1a9dce9db5..19df91e7ba 100644
--- a/examples/qos_sched/cfg_file.h
+++ b/examples/qos_sched/cfg_file.h
@@ -12,10 +12,8 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);
int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);
-#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p);
-#endif
int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);
diff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c
index 8a0fb8a374..0afd553283 100644
--- a/examples/qos_sched/init.c
+++ b/examples/qos_sched/init.c
@@ -201,7 +201,6 @@ static struct rte_sched_subport_profile_params
},
};
-#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
.cman_mode = RTE_SCHED_CMAN_RED,
.red_params = {
@@ -271,7 +270,6 @@ struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
{
@@ -281,9 +279,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
.n_pipe_profiles = sizeof(pipe_profiles) /
sizeof(struct rte_sched_pipe_params),
.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
},
};
diff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h
index 915311bac8..76a68f585f 100644
--- a/examples/qos_sched/main.h
+++ b/examples/qos_sched/main.h
@@ -153,9 +153,7 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
extern uint32_t n_active_queues;
extern struct rte_sched_port_params port_params;
-#ifdef RTE_SCHED_CMAN
extern struct rte_sched_cman_params cman_params;
-#endif
extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];
int app_parse_args(int argc, char **argv);
diff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg
index d4b21c0170..db65b0ed01 100644
--- a/examples/qos_sched/profile.cfg
+++ b/examples/qos_sched/profile.cfg
@@ -142,68 +142,68 @@ tc 12 wrr weights = 1 1 1 1
;tc 12 wred inv prob = 10 10 10
;tc 12 wred weight = 9 9 9
-[pie]
-tc 0 qdelay ref = 15
-tc 0 max burst = 150
-tc 0 update interval = 15
-tc 0 tailq th = 64
-
-tc 1 qdelay ref = 15
-tc 1 max burst = 150
-tc 1 update interval = 15
-tc 1 tailq th = 64
-
-tc 2 qdelay ref = 15
-tc 2 max burst = 150
-tc 2 update interval = 15
-tc 2 tailq th = 64
-
-tc 3 qdelay ref = 15
-tc 3 max burst = 150
-tc 3 update interval = 15
-tc 3 tailq th = 64
-
-tc 4 qdelay ref = 15
-tc 4 max burst = 150
-tc 4 update interval = 15
-tc 4 tailq th = 64
-
-tc 5 qdelay ref = 15
-tc 5 max burst = 150
-tc 5 update interval = 15
-tc 5 tailq th = 64
-
-tc 6 qdelay ref = 15
-tc 6 max burst = 150
-tc 6 update interval = 15
-tc 6 tailq th = 64
-
-tc 7 qdelay ref = 15
-tc 7 max burst = 150
-tc 7 update interval = 15
-tc 7 tailq th = 64
-
-tc 8 qdelay ref = 15
-tc 8 max burst = 150
-tc 8 update interval = 15
-tc 8 tailq th = 64
-
-tc 9 qdelay ref = 15
-tc 9 max burst = 150
-tc 9 update interval = 15
-tc 9 tailq th = 64
-
-tc 10 qdelay ref = 15
-tc 10 max burst = 150
-tc 10 update interval = 15
-tc 10 tailq th = 64
-
-tc 11 qdelay ref = 15
-tc 11 max burst = 150
-tc 11 update interval = 15
-tc 11 tailq th = 64
-
-tc 12 qdelay ref = 15
-tc 12 max burst = 150
-tc 12 update interval = 15
-tc 12 tailq th = 64
+;[pie]
+;tc 0 qdelay ref = 15
+;tc 0 max burst = 150
+;tc 0 update interval = 15
+;tc 0 tailq th = 64
+
+;tc 1 qdelay ref = 15
+;tc 1 max burst = 150
+;tc 1 update interval = 15
+;tc 1 tailq th = 64
+
+;tc 2 qdelay ref = 15
+;tc 2 max burst = 150
+;tc 2 update interval = 15
+;tc 2 tailq th = 64
+
+;tc 3 qdelay ref = 15
+;tc 3 max burst = 150
+;tc 3 update interval = 15
+;tc 3 tailq th = 64
+
+;tc 4 qdelay ref = 15
+;tc 4 max burst = 150
+;tc 4 update interval = 15
+;tc 4 tailq th = 64
+
+;tc 5 qdelay ref = 15
+;tc 5 max burst = 150
+;tc 5 update interval = 15
+;tc 5 tailq th = 64
+
+;tc 6 qdelay ref = 15
+;tc 6 max burst = 150
+;tc 6 update interval = 15
+;tc 6 tailq th = 64
+
+;tc 7 qdelay ref = 15
+;tc 7 max burst = 150
+;tc 7 update interval = 15
+;tc 7 tailq th = 64
+
+;tc 8 qdelay ref = 15
+;tc 8 max burst = 150
+;tc 8 update interval = 15
+;tc 8 tailq th = 64
+
+;tc 9 qdelay ref = 15
+;tc 9 max burst = 150
+;tc 9 update interval = 15
+;tc 9 tailq th = 64
+
+;tc 10 qdelay ref = 15
+;tc 10 max burst = 150
+;tc 10 update interval = 15
+;tc 10 tailq th = 64
+
+;tc 11 qdelay ref = 15
+;tc 11 max burst = 150
+;tc 11 update interval = 15
+;tc 11 tailq th = 64
+
+;tc 12 qdelay ref = 15
+;tc 12 max burst = 150
+;tc 12 update interval = 15
+;tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_pie.cfg b/examples/qos_sched/profile_pie.cfg
new file mode 100644
index 0000000000..241f748b33
--- /dev/null
+++ b/examples/qos_sched/profile_pie.cfg
@@ -0,0 +1,142 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+[pie]
+tc 0 qdelay ref = 15
+tc 0 max burst = 150
+tc 0 update interval = 15
+tc 0 tailq th = 64
+
+tc 1 qdelay ref = 15
+tc 1 max burst = 150
+tc 1 update interval = 15
+tc 1 tailq th = 64
+
+tc 2 qdelay ref = 15
+tc 2 max burst = 150
+tc 2 update interval = 15
+tc 2 tailq th = 64
+
+tc 3 qdelay ref = 15
+tc 3 max burst = 150
+tc 3 update interval = 15
+tc 3 tailq th = 64
+
+tc 4 qdelay ref = 15
+tc 4 max burst = 150
+tc 4 update interval = 15
+tc 4 tailq th = 64
+
+tc 5 qdelay ref = 15
+tc 5 max burst = 150
+tc 5 update interval = 15
+tc 5 tailq th = 64
+
+tc 6 qdelay ref = 15
+tc 6 max burst = 150
+tc 6 update interval = 15
+tc 6 tailq th = 64
+
+tc 7 qdelay ref = 15
+tc 7 max burst = 150
+tc 7 update interval = 15
+tc 7 tailq th = 64
+
+tc 8 qdelay ref = 15
+tc 8 max burst = 150
+tc 8 update interval = 15
+tc 8 tailq th = 64
+
+tc 9 qdelay ref = 15
+tc 9 max burst = 150
+tc 9 update interval = 15
+tc 9 tailq th = 64
+
+tc 10 qdelay ref = 15
+tc 10 max burst = 150
+tc 10 update interval = 15
+tc 10 tailq th = 64
+
+tc 11 qdelay ref = 15
+tc 11 max burst = 150
+tc 11 update interval = 15
+tc 11 tailq th = 64
+
+tc 12 qdelay ref = 15
+tc 12 max burst = 150
+tc 12 update interval = 15
+tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_red.cfg b/examples/qos_sched/profile_red.cfg
new file mode 100644
index 0000000000..4486d2799e
--- /dev/null
+++ b/examples/qos_sched/profile_red.cfg
@@ -0,0 +1,143 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+; RED params per traffic class and color (Green / Yellow / Red)
+[red]
+tc 0 wred min = 48 40 32
+tc 0 wred max = 64 64 64
+tc 0 wred inv prob = 10 10 10
+tc 0 wred weight = 9 9 9
+
+tc 1 wred min = 48 40 32
+tc 1 wred max = 64 64 64
+tc 1 wred inv prob = 10 10 10
+tc 1 wred weight = 9 9 9
+
+tc 2 wred min = 48 40 32
+tc 2 wred max = 64 64 64
+tc 2 wred inv prob = 10 10 10
+tc 2 wred weight = 9 9 9
+
+tc 3 wred min = 48 40 32
+tc 3 wred max = 64 64 64
+tc 3 wred inv prob = 10 10 10
+tc 3 wred weight = 9 9 9
+
+tc 4 wred min = 48 40 32
+tc 4 wred max = 64 64 64
+tc 4 wred inv prob = 10 10 10
+tc 4 wred weight = 9 9 9
+
+tc 5 wred min = 48 40 32
+tc 5 wred max = 64 64 64
+tc 5 wred inv prob = 10 10 10
+tc 5 wred weight = 9 9 9
+
+tc 6 wred min = 48 40 32
+tc 6 wred max = 64 64 64
+tc 6 wred inv prob = 10 10 10
+tc 6 wred weight = 9 9 9
+
+tc 7 wred min = 48 40 32
+tc 7 wred max = 64 64 64
+tc 7 wred inv prob = 10 10 10
+tc 7 wred weight = 9 9 9
+
+tc 8 wred min = 48 40 32
+tc 8 wred max = 64 64 64
+tc 8 wred inv prob = 10 10 10
+tc 8 wred weight = 9 9 9
+
+tc 9 wred min = 48 40 32
+tc 9 wred max = 64 64 64
+tc 9 wred inv prob = 10 10 10
+tc 9 wred weight = 9 9 9
+
+tc 10 wred min = 48 40 32
+tc 10 wred max = 64 64 64
+tc 10 wred inv prob = 10 10 10
+tc 10 wred weight = 9 9 9
+
+tc 11 wred min = 48 40 32
+tc 11 wred max = 64 64 64
+tc 11 wred inv prob = 10 10 10
+tc 11 wred weight = 9 9 9
+
+tc 12 wred min = 48 40 32
+tc 12 wred max = 64 64 64
+tc 12 wred inv prob = 10 10 10
+tc 12 wred weight = 9 9 9
diff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c
index ec74bee939..84c5e315c3 100644
--- a/lib/sched/rte_sched.c
+++ b/lib/sched/rte_sched.c
@@ -81,13 +81,11 @@ struct rte_sched_queue {
struct rte_sched_queue_extra {
struct rte_sched_queue_stats stats;
-#ifdef RTE_SCHED_CMAN
RTE_STD_C11
union {
struct rte_red red;
struct rte_pie pie;
};
-#endif
};
enum grinder_state {
@@ -179,7 +177,6 @@ struct rte_sched_subport {
/* Pipe queues size */
uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
-#ifdef RTE_SCHED_CMAN
bool cman_enabled;
enum rte_sched_cman_mode cman;
@@ -188,7 +185,6 @@ struct rte_sched_subport {
struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];
struct rte_pie_config pie_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
};
-#endif
/* Scheduling loop detection */
uint32_t pipe_loop;
@@ -1081,7 +1077,6 @@ rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports)
rte_free(port);
}
-#ifdef RTE_SCHED_CMAN
static int
rte_sched_red_config(struct rte_sched_port *port,
struct rte_sched_subport *s,
@@ -1163,7 +1158,6 @@ rte_sched_cman_config(struct rte_sched_port *port,
return -EINVAL;
}
-#endif
int
rte_sched_subport_config(struct rte_sched_port *port,
@@ -1254,7 +1248,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
s->n_pipe_profiles = params->n_pipe_profiles;
s->n_max_pipe_profiles = params->n_max_pipe_profiles;
-#ifdef RTE_SCHED_CMAN
if (params->cman_params != NULL) {
s->cman_enabled = true;
status = rte_sched_cman_config(port, s, params, n_subports);
@@ -1266,7 +1259,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
} else {
s->cman_enabled = false;
}
-#endif
/* Scheduling loop detection */
s->pipe_loop = RTE_SCHED_PIPE_INVALID;
@@ -1792,7 +1784,7 @@ rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
uint32_t tc_index = rte_sched_port_pipe_tc(port, qindex);
uint32_t pkt_len = pkt->pkt_len;
@@ -1818,21 +1810,17 @@ static inline void
rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
uint32_t pkt_len = pkt->pkt_len;
qe->stats.n_pkts_dropped += 1;
qe->stats.n_bytes_dropped += pkt_len;
-#ifdef RTE_SCHED_CMAN
if (subport->cman_enabled)
qe->stats.n_pkts_cman_dropped += n_pkts_cman_dropped;
-#endif
}
-#ifdef RTE_SCHED_CMAN
-
static inline int
rte_sched_port_cman_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
@@ -1877,13 +1865,11 @@ static inline void
rte_sched_port_red_set_queue_empty_timestamp(struct rte_sched_port *port,
struct rte_sched_subport *subport, uint32_t qindex)
{
- if (subport->cman_enabled) {
+ if (subport->cman_enabled && subport->cman == RTE_SCHED_CMAN_RED) {
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
- if (subport->cman == RTE_SCHED_CMAN_RED) {
- struct rte_red *red = &qe->red;
+ struct rte_red *red = &qe->red;
- rte_red_mark_queue_empty(red, port->time);
- }
+ rte_red_mark_queue_empty(red, port->time);
}
}
@@ -1902,29 +1888,6 @@ uint32_t qindex, uint32_t pkt_len, uint64_t time) {
}
}
-#else
-
-static inline int rte_sched_port_cman_drop(struct rte_sched_port *port __rte_unused,
- struct rte_sched_subport *subport __rte_unused,
- struct rte_mbuf *pkt __rte_unused,
- uint32_t qindex __rte_unused,
- uint16_t qlen __rte_unused)
-{
- return 0;
-}
-
-#define rte_sched_port_red_set_queue_empty_timestamp(port, subport, qindex)
-
-static inline void
-rte_sched_port_pie_dequeue(struct rte_sched_subport *subport __rte_unused,
- uint32_t qindex __rte_unused,
- uint32_t pkt_len __rte_unused,
- uint64_t time __rte_unused) {
- /* do-nothing when RTE_SCHED_CMAN not defined */
-}
-
-#endif /* RTE_SCHED_CMAN */
-
#ifdef RTE_SCHED_DEBUG
static inline void
--
2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v3] sched: enable CMAN at runtime
2022-06-08 9:42 ` [PATCH v3] " Marcin Danilewicz
@ 2022-06-08 11:59 ` Dumitrescu, Cristian
2022-06-08 15:29 ` Danilewicz, MarcinX
2022-06-13 9:09 ` [PATCH v4] " Marcin Danilewicz
1 sibling, 1 reply; 27+ messages in thread
From: Dumitrescu, Cristian @ 2022-06-08 11:59 UTC (permalink / raw)
To: Danilewicz, MarcinX, dev, Singh, Jasvinder; +Cc: Ajmera, Megha, Liu, Yu Y
> -----Original Message-----
> From: Danilewicz, MarcinX <marcinx.danilewicz@intel.com>
> Sent: Wednesday, June 8, 2022 10:42 AM
> To: dev@dpdk.org; Singh, Jasvinder <jasvinder.singh@intel.com>;
> Dumitrescu, Cristian <cristian.dumitrescu@intel.com>
> Cc: Ajmera, Megha <megha.ajmera@intel.com>
> Subject: [PATCH v3] sched: enable CMAN at runtime
>
> Added changes to enable CMAN (RED or PIE) at init
> from profile configuration file.
>
> By default CMAN code is enable but not in use, when
> there is no RED or PIE profile configured.
>
> Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
> ---
> Log: v2 change in rte_sched.h to avoid ABI breakage.
> v3 changes from comments
> ---
Marcin,
Your patch does not apply cleanly on top of DPDK main latest, can you please fix.
Regards,
Cristian
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v3] sched: enable CMAN at runtime
2022-06-08 11:59 ` Dumitrescu, Cristian
@ 2022-06-08 15:29 ` Danilewicz, MarcinX
0 siblings, 0 replies; 27+ messages in thread
From: Danilewicz, MarcinX @ 2022-06-08 15:29 UTC (permalink / raw)
To: Dumitrescu, Cristian, dev, Singh, Jasvinder; +Cc: Ajmera, Megha, Liu, Yu Y
Hi Cristian,
Ok, let me check.
BR,
/Marcin
> -----Original Message-----
> From: Dumitrescu, Cristian <cristian.dumitrescu@intel.com>
> Sent: Wednesday, June 8, 2022 1:59 PM
> To: Danilewicz, MarcinX <marcinx.danilewicz@intel.com>; dev@dpdk.org;
> Singh, Jasvinder <jasvinder.singh@intel.com>
> Cc: Ajmera, Megha <megha.ajmera@intel.com>; Liu, Yu Y
> <yu.y.liu@intel.com>
> Subject: RE: [PATCH v3] sched: enable CMAN at runtime
>
>
>
> > -----Original Message-----
> > From: Danilewicz, MarcinX <marcinx.danilewicz@intel.com>
> > Sent: Wednesday, June 8, 2022 10:42 AM
> > To: dev@dpdk.org; Singh, Jasvinder <jasvinder.singh@intel.com>;
> > Dumitrescu, Cristian <cristian.dumitrescu@intel.com>
> > Cc: Ajmera, Megha <megha.ajmera@intel.com>
> > Subject: [PATCH v3] sched: enable CMAN at runtime
> >
> > Added changes to enable CMAN (RED or PIE) at init from profile
> > configuration file.
> >
> > By default CMAN code is enable but not in use, when there is no RED or
> > PIE profile configured.
> >
> > Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
> > ---
> > Log: v2 change in rte_sched.h to avoid ABI breakage.
> > v3 changes from comments
> > ---
>
> Marcin,
>
> Your patch does not apply cleanly on top of DPDK main latest, can you please
> fix.
>
> Regards,
> Cristian
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v4] sched: enable CMAN at runtime
2022-06-08 9:42 ` [PATCH v3] " Marcin Danilewicz
2022-06-08 11:59 ` Dumitrescu, Cristian
@ 2022-06-13 9:09 ` Marcin Danilewicz
2022-06-17 11:48 ` Dumitrescu, Cristian
2022-06-20 13:56 ` [PATCH v5] ched: " Marcin Danilewicz
1 sibling, 2 replies; 27+ messages in thread
From: Marcin Danilewicz @ 2022-06-13 9:09 UTC (permalink / raw)
To: dev, jasvinder.singh, cristian.dumitrescu; +Cc: megha.ajmera
Added changes to enable CMAN (RED or PIE) at init
from profile configuration file.
By default CMAN code is enable but not in use, when
there is no RED or PIE profile configured.
Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
---
Log: v2 change in rte_sched.h to avoid ABI breakage.
v3 changes from comments
---
config/rte_config.h | 3 -
drivers/net/softnic/rte_eth_softnic_tm.c | 12 --
examples/ip_pipeline/tmgr.c | 4 -
examples/qos_sched/cfg_file.c | 11 +-
examples/qos_sched/cfg_file.h | 2 -
examples/qos_sched/init.c | 4 -
examples/qos_sched/main.h | 2 -
examples/qos_sched/profile.cfg | 130 ++++++++++-----------
examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++
examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++
lib/sched/rte_sched.c | 47 +-------
11 files changed, 359 insertions(+), 141 deletions(-)
create mode 100644 examples/qos_sched/profile_pie.cfg
create mode 100644 examples/qos_sched/profile_red.cfg
diff --git a/config/rte_config.h b/config/rte_config.h
index 8eb29c1525..1740a1d053 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -88,9 +88,6 @@
/* rte_power defines */
#define RTE_MAX_LCORE_FREQS 64
-/* rte_sched defines */
-#undef RTE_SCHED_CMAN
-
/* rte_graph defines */
#define RTE_GRAPH_BURST_SIZE 256
#define RTE_LIBRTE_GRAPH_STATS 1
diff --git a/drivers/net/softnic/rte_eth_softnic_tm.c b/drivers/net/softnic/rte_eth_softnic_tm.c
index 6a7766ba1c..3a5fd676e9 100644
--- a/drivers/net/softnic/rte_eth_softnic_tm.c
+++ b/drivers/net/softnic/rte_eth_softnic_tm.c
@@ -420,11 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,
return 0;
}
-#ifdef RTE_SCHED_CMAN
#define WRED_SUPPORTED 1
-#else
-#define WRED_SUPPORTED 0
-#endif
#define STATS_MASK_DEFAULT \
(RTE_TM_STATS_N_PKTS | \
@@ -2300,8 +2296,6 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev, uint32_t tc_id)
return NULL;
}
-#ifdef RTE_SCHED_CMAN
-
static void
wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
{
@@ -2325,12 +2319,6 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
}
}
-#else
-
-#define wred_profiles_set(dev, subport_id)
-
-#endif
-
static struct tm_shared_shaper *
tm_tc_shared_shaper_get(struct rte_eth_dev *dev, struct tm_node *tc_node)
{
diff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c
index b138e885cf..e68e9961be 100644
--- a/examples/ip_pipeline/tmgr.c
+++ b/examples/ip_pipeline/tmgr.c
@@ -17,7 +17,6 @@ static uint32_t n_subport_profiles;
static struct rte_sched_pipe_params
pipe_profile[TMGR_PIPE_PROFILE_MAX];
-#ifdef RTE_SCHED_CMAN
static struct rte_sched_cman_params cman_params = {
.red_params = {
/* Traffic Class 0 Colors Green / Yellow / Red */
@@ -86,7 +85,6 @@ static struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
static uint32_t n_pipe_profiles;
@@ -96,9 +94,7 @@ static const struct rte_sched_subport_params subport_params_default = {
.pipe_profiles = pipe_profile,
.n_pipe_profiles = 0, /* filled at run time */
.n_max_pipe_profiles = RTE_DIM(pipe_profile),
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
};
static struct tmgr_port_list tmgr_port_list;
diff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c
index 450482f07d..3284b4d252 100644
--- a/examples/qos_sched/cfg_file.c
+++ b/examples/qos_sched/cfg_file.c
@@ -229,11 +229,14 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg,
return 0;
}
-#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p)
{
int j, k;
+
+ if (subport_p->cman_params != NULL)
+ return;
+
subport_p->cman_params->cman_mode = cman_p.cman_mode;
for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
@@ -261,7 +264,6 @@ void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
}
}
}
-#endif
int
cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)
@@ -276,9 +278,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
memset(active_queues, 0, sizeof(active_queues));
n_active_queues = 0;
-#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
- .cman_mode = RTE_SCHED_CMAN_RED,
.red_params = { },
};
@@ -387,7 +387,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
-#endif /* RTE_SCHED_CMAN */
for (i = 0; i < MAX_SCHED_SUBPORTS; i++) {
char sec_name[CFG_NAME_LEN];
@@ -465,9 +464,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
}
-#ifdef RTE_SCHED_CMAN
set_subport_cman_params(subport_params+i, cman_params);
-#endif
}
}
diff --git a/examples/qos_sched/cfg_file.h b/examples/qos_sched/cfg_file.h
index 1a9dce9db5..19df91e7ba 100644
--- a/examples/qos_sched/cfg_file.h
+++ b/examples/qos_sched/cfg_file.h
@@ -12,10 +12,8 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);
int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);
-#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p);
-#endif
int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);
diff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c
index 8a0fb8a374..0afd553283 100644
--- a/examples/qos_sched/init.c
+++ b/examples/qos_sched/init.c
@@ -201,7 +201,6 @@ static struct rte_sched_subport_profile_params
},
};
-#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
.cman_mode = RTE_SCHED_CMAN_RED,
.red_params = {
@@ -271,7 +270,6 @@ struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
{
@@ -281,9 +279,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
.n_pipe_profiles = sizeof(pipe_profiles) /
sizeof(struct rte_sched_pipe_params),
.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
},
};
diff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h
index 915311bac8..76a68f585f 100644
--- a/examples/qos_sched/main.h
+++ b/examples/qos_sched/main.h
@@ -153,9 +153,7 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
extern uint32_t n_active_queues;
extern struct rte_sched_port_params port_params;
-#ifdef RTE_SCHED_CMAN
extern struct rte_sched_cman_params cman_params;
-#endif
extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];
int app_parse_args(int argc, char **argv);
diff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg
index d4b21c0170..db65b0ed01 100644
--- a/examples/qos_sched/profile.cfg
+++ b/examples/qos_sched/profile.cfg
@@ -142,68 +142,68 @@ tc 12 wrr weights = 1 1 1 1
;tc 12 wred inv prob = 10 10 10
;tc 12 wred weight = 9 9 9
-[pie]
-tc 0 qdelay ref = 15
-tc 0 max burst = 150
-tc 0 update interval = 15
-tc 0 tailq th = 64
-
-tc 1 qdelay ref = 15
-tc 1 max burst = 150
-tc 1 update interval = 15
-tc 1 tailq th = 64
-
-tc 2 qdelay ref = 15
-tc 2 max burst = 150
-tc 2 update interval = 15
-tc 2 tailq th = 64
-
-tc 3 qdelay ref = 15
-tc 3 max burst = 150
-tc 3 update interval = 15
-tc 3 tailq th = 64
-
-tc 4 qdelay ref = 15
-tc 4 max burst = 150
-tc 4 update interval = 15
-tc 4 tailq th = 64
-
-tc 5 qdelay ref = 15
-tc 5 max burst = 150
-tc 5 update interval = 15
-tc 5 tailq th = 64
-
-tc 6 qdelay ref = 15
-tc 6 max burst = 150
-tc 6 update interval = 15
-tc 6 tailq th = 64
-
-tc 7 qdelay ref = 15
-tc 7 max burst = 150
-tc 7 update interval = 15
-tc 7 tailq th = 64
-
-tc 8 qdelay ref = 15
-tc 8 max burst = 150
-tc 8 update interval = 15
-tc 8 tailq th = 64
-
-tc 9 qdelay ref = 15
-tc 9 max burst = 150
-tc 9 update interval = 15
-tc 9 tailq th = 64
-
-tc 10 qdelay ref = 15
-tc 10 max burst = 150
-tc 10 update interval = 15
-tc 10 tailq th = 64
-
-tc 11 qdelay ref = 15
-tc 11 max burst = 150
-tc 11 update interval = 15
-tc 11 tailq th = 64
-
-tc 12 qdelay ref = 15
-tc 12 max burst = 150
-tc 12 update interval = 15
-tc 12 tailq th = 64
+;[pie]
+;tc 0 qdelay ref = 15
+;tc 0 max burst = 150
+;tc 0 update interval = 15
+;tc 0 tailq th = 64
+
+;tc 1 qdelay ref = 15
+;tc 1 max burst = 150
+;tc 1 update interval = 15
+;tc 1 tailq th = 64
+
+;tc 2 qdelay ref = 15
+;tc 2 max burst = 150
+;tc 2 update interval = 15
+;tc 2 tailq th = 64
+
+;tc 3 qdelay ref = 15
+;tc 3 max burst = 150
+;tc 3 update interval = 15
+;tc 3 tailq th = 64
+
+;tc 4 qdelay ref = 15
+;tc 4 max burst = 150
+;tc 4 update interval = 15
+;tc 4 tailq th = 64
+
+;tc 5 qdelay ref = 15
+;tc 5 max burst = 150
+;tc 5 update interval = 15
+;tc 5 tailq th = 64
+
+;tc 6 qdelay ref = 15
+;tc 6 max burst = 150
+;tc 6 update interval = 15
+;tc 6 tailq th = 64
+
+;tc 7 qdelay ref = 15
+;tc 7 max burst = 150
+;tc 7 update interval = 15
+;tc 7 tailq th = 64
+
+;tc 8 qdelay ref = 15
+;tc 8 max burst = 150
+;tc 8 update interval = 15
+;tc 8 tailq th = 64
+
+;tc 9 qdelay ref = 15
+;tc 9 max burst = 150
+;tc 9 update interval = 15
+;tc 9 tailq th = 64
+
+;tc 10 qdelay ref = 15
+;tc 10 max burst = 150
+;tc 10 update interval = 15
+;tc 10 tailq th = 64
+
+;tc 11 qdelay ref = 15
+;tc 11 max burst = 150
+;tc 11 update interval = 15
+;tc 11 tailq th = 64
+
+;tc 12 qdelay ref = 15
+;tc 12 max burst = 150
+;tc 12 update interval = 15
+;tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_pie.cfg b/examples/qos_sched/profile_pie.cfg
new file mode 100644
index 0000000000..241f748b33
--- /dev/null
+++ b/examples/qos_sched/profile_pie.cfg
@@ -0,0 +1,142 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+[pie]
+tc 0 qdelay ref = 15
+tc 0 max burst = 150
+tc 0 update interval = 15
+tc 0 tailq th = 64
+
+tc 1 qdelay ref = 15
+tc 1 max burst = 150
+tc 1 update interval = 15
+tc 1 tailq th = 64
+
+tc 2 qdelay ref = 15
+tc 2 max burst = 150
+tc 2 update interval = 15
+tc 2 tailq th = 64
+
+tc 3 qdelay ref = 15
+tc 3 max burst = 150
+tc 3 update interval = 15
+tc 3 tailq th = 64
+
+tc 4 qdelay ref = 15
+tc 4 max burst = 150
+tc 4 update interval = 15
+tc 4 tailq th = 64
+
+tc 5 qdelay ref = 15
+tc 5 max burst = 150
+tc 5 update interval = 15
+tc 5 tailq th = 64
+
+tc 6 qdelay ref = 15
+tc 6 max burst = 150
+tc 6 update interval = 15
+tc 6 tailq th = 64
+
+tc 7 qdelay ref = 15
+tc 7 max burst = 150
+tc 7 update interval = 15
+tc 7 tailq th = 64
+
+tc 8 qdelay ref = 15
+tc 8 max burst = 150
+tc 8 update interval = 15
+tc 8 tailq th = 64
+
+tc 9 qdelay ref = 15
+tc 9 max burst = 150
+tc 9 update interval = 15
+tc 9 tailq th = 64
+
+tc 10 qdelay ref = 15
+tc 10 max burst = 150
+tc 10 update interval = 15
+tc 10 tailq th = 64
+
+tc 11 qdelay ref = 15
+tc 11 max burst = 150
+tc 11 update interval = 15
+tc 11 tailq th = 64
+
+tc 12 qdelay ref = 15
+tc 12 max burst = 150
+tc 12 update interval = 15
+tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_red.cfg b/examples/qos_sched/profile_red.cfg
new file mode 100644
index 0000000000..4486d2799e
--- /dev/null
+++ b/examples/qos_sched/profile_red.cfg
@@ -0,0 +1,143 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+; RED params per traffic class and color (Green / Yellow / Red)
+[red]
+tc 0 wred min = 48 40 32
+tc 0 wred max = 64 64 64
+tc 0 wred inv prob = 10 10 10
+tc 0 wred weight = 9 9 9
+
+tc 1 wred min = 48 40 32
+tc 1 wred max = 64 64 64
+tc 1 wred inv prob = 10 10 10
+tc 1 wred weight = 9 9 9
+
+tc 2 wred min = 48 40 32
+tc 2 wred max = 64 64 64
+tc 2 wred inv prob = 10 10 10
+tc 2 wred weight = 9 9 9
+
+tc 3 wred min = 48 40 32
+tc 3 wred max = 64 64 64
+tc 3 wred inv prob = 10 10 10
+tc 3 wred weight = 9 9 9
+
+tc 4 wred min = 48 40 32
+tc 4 wred max = 64 64 64
+tc 4 wred inv prob = 10 10 10
+tc 4 wred weight = 9 9 9
+
+tc 5 wred min = 48 40 32
+tc 5 wred max = 64 64 64
+tc 5 wred inv prob = 10 10 10
+tc 5 wred weight = 9 9 9
+
+tc 6 wred min = 48 40 32
+tc 6 wred max = 64 64 64
+tc 6 wred inv prob = 10 10 10
+tc 6 wred weight = 9 9 9
+
+tc 7 wred min = 48 40 32
+tc 7 wred max = 64 64 64
+tc 7 wred inv prob = 10 10 10
+tc 7 wred weight = 9 9 9
+
+tc 8 wred min = 48 40 32
+tc 8 wred max = 64 64 64
+tc 8 wred inv prob = 10 10 10
+tc 8 wred weight = 9 9 9
+
+tc 9 wred min = 48 40 32
+tc 9 wred max = 64 64 64
+tc 9 wred inv prob = 10 10 10
+tc 9 wred weight = 9 9 9
+
+tc 10 wred min = 48 40 32
+tc 10 wred max = 64 64 64
+tc 10 wred inv prob = 10 10 10
+tc 10 wred weight = 9 9 9
+
+tc 11 wred min = 48 40 32
+tc 11 wred max = 64 64 64
+tc 11 wred inv prob = 10 10 10
+tc 11 wred weight = 9 9 9
+
+tc 12 wred min = 48 40 32
+tc 12 wred max = 64 64 64
+tc 12 wred inv prob = 10 10 10
+tc 12 wred weight = 9 9 9
diff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c
index 599c7e9536..c5fa9e4582 100644
--- a/lib/sched/rte_sched.c
+++ b/lib/sched/rte_sched.c
@@ -81,13 +81,11 @@ struct rte_sched_queue {
struct rte_sched_queue_extra {
struct rte_sched_queue_stats stats;
-#ifdef RTE_SCHED_CMAN
RTE_STD_C11
union {
struct rte_red red;
struct rte_pie pie;
};
-#endif
};
enum grinder_state {
@@ -179,7 +177,6 @@ struct rte_sched_subport {
/* Pipe queues size */
uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
-#ifdef RTE_SCHED_CMAN
bool cman_enabled;
enum rte_sched_cman_mode cman;
@@ -188,7 +185,6 @@ struct rte_sched_subport {
struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];
struct rte_pie_config pie_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
};
-#endif
/* Scheduling loop detection */
uint32_t pipe_loop;
@@ -1084,7 +1080,6 @@ rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports)
rte_free(port);
}
-#ifdef RTE_SCHED_CMAN
static int
rte_sched_red_config(struct rte_sched_port *port,
struct rte_sched_subport *s,
@@ -1166,7 +1161,6 @@ rte_sched_cman_config(struct rte_sched_port *port,
return -EINVAL;
}
-#endif
int
rte_sched_subport_tc_ov_config(struct rte_sched_port *port,
@@ -1285,7 +1279,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
/* TC oversubscription is enabled by default */
s->tc_ov_enabled = 1;
-#ifdef RTE_SCHED_CMAN
if (params->cman_params != NULL) {
s->cman_enabled = true;
status = rte_sched_cman_config(port, s, params, n_subports);
@@ -1297,7 +1290,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
} else {
s->cman_enabled = false;
}
-#endif
/* Scheduling loop detection */
s->pipe_loop = RTE_SCHED_PIPE_INVALID;
@@ -1823,7 +1815,7 @@ rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
uint32_t tc_index = rte_sched_port_pipe_tc(port, qindex);
uint32_t pkt_len = pkt->pkt_len;
@@ -1849,21 +1841,17 @@ static inline void
rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
uint32_t pkt_len = pkt->pkt_len;
qe->stats.n_pkts_dropped += 1;
qe->stats.n_bytes_dropped += pkt_len;
-#ifdef RTE_SCHED_CMAN
if (subport->cman_enabled)
qe->stats.n_pkts_cman_dropped += n_pkts_cman_dropped;
-#endif
}
-#ifdef RTE_SCHED_CMAN
-
static inline int
rte_sched_port_cman_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
@@ -1908,13 +1896,11 @@ static inline void
rte_sched_port_red_set_queue_empty_timestamp(struct rte_sched_port *port,
struct rte_sched_subport *subport, uint32_t qindex)
{
- if (subport->cman_enabled) {
+ if (subport->cman_enabled && subport->cman == RTE_SCHED_CMAN_RED) {
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
- if (subport->cman == RTE_SCHED_CMAN_RED) {
- struct rte_red *red = &qe->red;
+ struct rte_red *red = &qe->red;
- rte_red_mark_queue_empty(red, port->time);
- }
+ rte_red_mark_queue_empty(red, port->time);
}
}
@@ -1933,29 +1919,6 @@ uint32_t qindex, uint32_t pkt_len, uint64_t time) {
}
}
-#else
-
-static inline int rte_sched_port_cman_drop(struct rte_sched_port *port __rte_unused,
- struct rte_sched_subport *subport __rte_unused,
- struct rte_mbuf *pkt __rte_unused,
- uint32_t qindex __rte_unused,
- uint16_t qlen __rte_unused)
-{
- return 0;
-}
-
-#define rte_sched_port_red_set_queue_empty_timestamp(port, subport, qindex)
-
-static inline void
-rte_sched_port_pie_dequeue(struct rte_sched_subport *subport __rte_unused,
- uint32_t qindex __rte_unused,
- uint32_t pkt_len __rte_unused,
- uint64_t time __rte_unused) {
- /* do-nothing when RTE_SCHED_CMAN not defined */
-}
-
-#endif /* RTE_SCHED_CMAN */
-
#ifdef RTE_SCHED_DEBUG
static inline void
--
2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v4] sched: enable CMAN at runtime
2022-06-13 9:09 ` [PATCH v4] " Marcin Danilewicz
@ 2022-06-17 11:48 ` Dumitrescu, Cristian
2022-06-20 13:56 ` [PATCH v5] ched: " Marcin Danilewicz
1 sibling, 0 replies; 27+ messages in thread
From: Dumitrescu, Cristian @ 2022-06-17 11:48 UTC (permalink / raw)
To: Danilewicz, MarcinX, dev, Singh, Jasvinder; +Cc: Ajmera, Megha, Liu, Yu Y
> -----Original Message-----
> From: Danilewicz, MarcinX <marcinx.danilewicz@intel.com>
> Sent: Monday, June 13, 2022 10:09 AM
> To: dev@dpdk.org; Singh, Jasvinder <jasvinder.singh@intel.com>;
> Dumitrescu, Cristian <cristian.dumitrescu@intel.com>
> Cc: Ajmera, Megha <megha.ajmera@intel.com>
> Subject: [PATCH v4] sched: enable CMAN at runtime
>
> Added changes to enable CMAN (RED or PIE) at init
> from profile configuration file.
>
> By default CMAN code is enable but not in use, when
> there is no RED or PIE profile configured.
>
> Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
> ---
> Log: v2 change in rte_sched.h to avoid ABI breakage.
> v3 changes from comments
> ---
> config/rte_config.h | 3 -
> drivers/net/softnic/rte_eth_softnic_tm.c | 12 --
> examples/ip_pipeline/tmgr.c | 4 -
> examples/qos_sched/cfg_file.c | 11 +-
> examples/qos_sched/cfg_file.h | 2 -
> examples/qos_sched/init.c | 4 -
> examples/qos_sched/main.h | 2 -
> examples/qos_sched/profile.cfg | 130 ++++++++++-----------
> examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++
> examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++
> lib/sched/rte_sched.c | 47 +-------
> 11 files changed, 359 insertions(+), 141 deletions(-)
> create mode 100644 examples/qos_sched/profile_pie.cfg
> create mode 100644 examples/qos_sched/profile_red.cfg
>
Marcin,
Code changes look good to me, but still not able to cleanly apply this patch on top of DPDK latest with git am, can you please make sure this gets fixed?
Applying: sched: enable CMAN at runtime
error: patch failed: config/rte_config.h:88
error: config/rte_config.h: patch does not apply
Patch failed at 0001 sched: enable CMAN at runtime
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Regards,
Cristian
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v5] ched: enable CMAN at runtime
2022-06-13 9:09 ` [PATCH v4] " Marcin Danilewicz
2022-06-17 11:48 ` Dumitrescu, Cristian
@ 2022-06-20 13:56 ` Marcin Danilewicz
2022-06-20 14:49 ` Dumitrescu, Cristian
2022-06-21 8:16 ` [PATCH v6] sched: " Marcin Danilewicz
1 sibling, 2 replies; 27+ messages in thread
From: Marcin Danilewicz @ 2022-06-20 13:56 UTC (permalink / raw)
To: dev, jasvinder.singh, cristian.dumitrescu; +Cc: megha.ajmera
Added changes to enable CMAN (RED or PIE) at init
from profile configuration file.
By default CMAN code is enable but not in use, when
there is no RED or PIE profile configured.
Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
---
Log: v2 change in rte_sched.h to avoid ABI breakage.
v3 changes from comments
v4 rebase to 22.07-rc1
v5 rebase to main latest
---
config/rte_config.h | 3 -
drivers/net/softnic/rte_eth_softnic_tm.c | 12 --
examples/ip_pipeline/tmgr.c | 4 -
examples/qos_sched/cfg_file.c | 11 +-
examples/qos_sched/cfg_file.h | 2 -
examples/qos_sched/init.c | 4 -
examples/qos_sched/main.h | 2 -
examples/qos_sched/profile.cfg | 130 ++++++++++-----------
examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++
examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++
lib/sched/rte_sched.c | 47 +-------
11 files changed, 359 insertions(+), 141 deletions(-)
create mode 100644 examples/qos_sched/profile_pie.cfg
create mode 100644 examples/qos_sched/profile_red.cfg
diff --git a/config/rte_config.h b/config/rte_config.h
index 46549cb062..ae56a86394 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -88,9 +88,6 @@
/* rte_power defines */
#define RTE_MAX_LCORE_FREQS 64
-/* rte_sched defines */
-// RTE_SCHED_CMAN is not set
-
/* rte_graph defines */
#define RTE_GRAPH_BURST_SIZE 256
#define RTE_LIBRTE_GRAPH_STATS 1
diff --git a/drivers/net/softnic/rte_eth_softnic_tm.c b/drivers/net/softnic/rte_eth_softnic_tm.c
index 6a7766ba1c..3a5fd676e9 100644
--- a/drivers/net/softnic/rte_eth_softnic_tm.c
+++ b/drivers/net/softnic/rte_eth_softnic_tm.c
@@ -420,11 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,
return 0;
}
-#ifdef RTE_SCHED_CMAN
#define WRED_SUPPORTED 1
-#else
-#define WRED_SUPPORTED 0
-#endif
#define STATS_MASK_DEFAULT \
(RTE_TM_STATS_N_PKTS | \
@@ -2300,8 +2296,6 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev, uint32_t tc_id)
return NULL;
}
-#ifdef RTE_SCHED_CMAN
-
static void
wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
{
@@ -2325,12 +2319,6 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
}
}
-#else
-
-#define wred_profiles_set(dev, subport_id)
-
-#endif
-
static struct tm_shared_shaper *
tm_tc_shared_shaper_get(struct rte_eth_dev *dev, struct tm_node *tc_node)
{
diff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c
index b138e885cf..e68e9961be 100644
--- a/examples/ip_pipeline/tmgr.c
+++ b/examples/ip_pipeline/tmgr.c
@@ -17,7 +17,6 @@ static uint32_t n_subport_profiles;
static struct rte_sched_pipe_params
pipe_profile[TMGR_PIPE_PROFILE_MAX];
-#ifdef RTE_SCHED_CMAN
static struct rte_sched_cman_params cman_params = {
.red_params = {
/* Traffic Class 0 Colors Green / Yellow / Red */
@@ -86,7 +85,6 @@ static struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
static uint32_t n_pipe_profiles;
@@ -96,9 +94,7 @@ static const struct rte_sched_subport_params subport_params_default = {
.pipe_profiles = pipe_profile,
.n_pipe_profiles = 0, /* filled at run time */
.n_max_pipe_profiles = RTE_DIM(pipe_profile),
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
};
static struct tmgr_port_list tmgr_port_list;
diff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c
index 450482f07d..3284b4d252 100644
--- a/examples/qos_sched/cfg_file.c
+++ b/examples/qos_sched/cfg_file.c
@@ -229,11 +229,14 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg,
return 0;
}
-#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p)
{
int j, k;
+
+ if (subport_p->cman_params != NULL)
+ return;
+
subport_p->cman_params->cman_mode = cman_p.cman_mode;
for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
@@ -261,7 +264,6 @@ void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
}
}
}
-#endif
int
cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)
@@ -276,9 +278,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
memset(active_queues, 0, sizeof(active_queues));
n_active_queues = 0;
-#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
- .cman_mode = RTE_SCHED_CMAN_RED,
.red_params = { },
};
@@ -387,7 +387,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
-#endif /* RTE_SCHED_CMAN */
for (i = 0; i < MAX_SCHED_SUBPORTS; i++) {
char sec_name[CFG_NAME_LEN];
@@ -465,9 +464,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
}
-#ifdef RTE_SCHED_CMAN
set_subport_cman_params(subport_params+i, cman_params);
-#endif
}
}
diff --git a/examples/qos_sched/cfg_file.h b/examples/qos_sched/cfg_file.h
index 1a9dce9db5..19df91e7ba 100644
--- a/examples/qos_sched/cfg_file.h
+++ b/examples/qos_sched/cfg_file.h
@@ -12,10 +12,8 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);
int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);
-#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p);
-#endif
int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);
diff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c
index 8a0fb8a374..0afd553283 100644
--- a/examples/qos_sched/init.c
+++ b/examples/qos_sched/init.c
@@ -201,7 +201,6 @@ static struct rte_sched_subport_profile_params
},
};
-#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
.cman_mode = RTE_SCHED_CMAN_RED,
.red_params = {
@@ -271,7 +270,6 @@ struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
{
@@ -281,9 +279,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
.n_pipe_profiles = sizeof(pipe_profiles) /
sizeof(struct rte_sched_pipe_params),
.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
},
};
diff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h
index 915311bac8..76a68f585f 100644
--- a/examples/qos_sched/main.h
+++ b/examples/qos_sched/main.h
@@ -153,9 +153,7 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
extern uint32_t n_active_queues;
extern struct rte_sched_port_params port_params;
-#ifdef RTE_SCHED_CMAN
extern struct rte_sched_cman_params cman_params;
-#endif
extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];
int app_parse_args(int argc, char **argv);
diff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg
index d4b21c0170..db65b0ed01 100644
--- a/examples/qos_sched/profile.cfg
+++ b/examples/qos_sched/profile.cfg
@@ -142,68 +142,68 @@ tc 12 wrr weights = 1 1 1 1
;tc 12 wred inv prob = 10 10 10
;tc 12 wred weight = 9 9 9
-[pie]
-tc 0 qdelay ref = 15
-tc 0 max burst = 150
-tc 0 update interval = 15
-tc 0 tailq th = 64
-
-tc 1 qdelay ref = 15
-tc 1 max burst = 150
-tc 1 update interval = 15
-tc 1 tailq th = 64
-
-tc 2 qdelay ref = 15
-tc 2 max burst = 150
-tc 2 update interval = 15
-tc 2 tailq th = 64
-
-tc 3 qdelay ref = 15
-tc 3 max burst = 150
-tc 3 update interval = 15
-tc 3 tailq th = 64
-
-tc 4 qdelay ref = 15
-tc 4 max burst = 150
-tc 4 update interval = 15
-tc 4 tailq th = 64
-
-tc 5 qdelay ref = 15
-tc 5 max burst = 150
-tc 5 update interval = 15
-tc 5 tailq th = 64
-
-tc 6 qdelay ref = 15
-tc 6 max burst = 150
-tc 6 update interval = 15
-tc 6 tailq th = 64
-
-tc 7 qdelay ref = 15
-tc 7 max burst = 150
-tc 7 update interval = 15
-tc 7 tailq th = 64
-
-tc 8 qdelay ref = 15
-tc 8 max burst = 150
-tc 8 update interval = 15
-tc 8 tailq th = 64
-
-tc 9 qdelay ref = 15
-tc 9 max burst = 150
-tc 9 update interval = 15
-tc 9 tailq th = 64
-
-tc 10 qdelay ref = 15
-tc 10 max burst = 150
-tc 10 update interval = 15
-tc 10 tailq th = 64
-
-tc 11 qdelay ref = 15
-tc 11 max burst = 150
-tc 11 update interval = 15
-tc 11 tailq th = 64
-
-tc 12 qdelay ref = 15
-tc 12 max burst = 150
-tc 12 update interval = 15
-tc 12 tailq th = 64
+;[pie]
+;tc 0 qdelay ref = 15
+;tc 0 max burst = 150
+;tc 0 update interval = 15
+;tc 0 tailq th = 64
+
+;tc 1 qdelay ref = 15
+;tc 1 max burst = 150
+;tc 1 update interval = 15
+;tc 1 tailq th = 64
+
+;tc 2 qdelay ref = 15
+;tc 2 max burst = 150
+;tc 2 update interval = 15
+;tc 2 tailq th = 64
+
+;tc 3 qdelay ref = 15
+;tc 3 max burst = 150
+;tc 3 update interval = 15
+;tc 3 tailq th = 64
+
+;tc 4 qdelay ref = 15
+;tc 4 max burst = 150
+;tc 4 update interval = 15
+;tc 4 tailq th = 64
+
+;tc 5 qdelay ref = 15
+;tc 5 max burst = 150
+;tc 5 update interval = 15
+;tc 5 tailq th = 64
+
+;tc 6 qdelay ref = 15
+;tc 6 max burst = 150
+;tc 6 update interval = 15
+;tc 6 tailq th = 64
+
+;tc 7 qdelay ref = 15
+;tc 7 max burst = 150
+;tc 7 update interval = 15
+;tc 7 tailq th = 64
+
+;tc 8 qdelay ref = 15
+;tc 8 max burst = 150
+;tc 8 update interval = 15
+;tc 8 tailq th = 64
+
+;tc 9 qdelay ref = 15
+;tc 9 max burst = 150
+;tc 9 update interval = 15
+;tc 9 tailq th = 64
+
+;tc 10 qdelay ref = 15
+;tc 10 max burst = 150
+;tc 10 update interval = 15
+;tc 10 tailq th = 64
+
+;tc 11 qdelay ref = 15
+;tc 11 max burst = 150
+;tc 11 update interval = 15
+;tc 11 tailq th = 64
+
+;tc 12 qdelay ref = 15
+;tc 12 max burst = 150
+;tc 12 update interval = 15
+;tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_pie.cfg b/examples/qos_sched/profile_pie.cfg
new file mode 100644
index 0000000000..241f748b33
--- /dev/null
+++ b/examples/qos_sched/profile_pie.cfg
@@ -0,0 +1,142 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+[pie]
+tc 0 qdelay ref = 15
+tc 0 max burst = 150
+tc 0 update interval = 15
+tc 0 tailq th = 64
+
+tc 1 qdelay ref = 15
+tc 1 max burst = 150
+tc 1 update interval = 15
+tc 1 tailq th = 64
+
+tc 2 qdelay ref = 15
+tc 2 max burst = 150
+tc 2 update interval = 15
+tc 2 tailq th = 64
+
+tc 3 qdelay ref = 15
+tc 3 max burst = 150
+tc 3 update interval = 15
+tc 3 tailq th = 64
+
+tc 4 qdelay ref = 15
+tc 4 max burst = 150
+tc 4 update interval = 15
+tc 4 tailq th = 64
+
+tc 5 qdelay ref = 15
+tc 5 max burst = 150
+tc 5 update interval = 15
+tc 5 tailq th = 64
+
+tc 6 qdelay ref = 15
+tc 6 max burst = 150
+tc 6 update interval = 15
+tc 6 tailq th = 64
+
+tc 7 qdelay ref = 15
+tc 7 max burst = 150
+tc 7 update interval = 15
+tc 7 tailq th = 64
+
+tc 8 qdelay ref = 15
+tc 8 max burst = 150
+tc 8 update interval = 15
+tc 8 tailq th = 64
+
+tc 9 qdelay ref = 15
+tc 9 max burst = 150
+tc 9 update interval = 15
+tc 9 tailq th = 64
+
+tc 10 qdelay ref = 15
+tc 10 max burst = 150
+tc 10 update interval = 15
+tc 10 tailq th = 64
+
+tc 11 qdelay ref = 15
+tc 11 max burst = 150
+tc 11 update interval = 15
+tc 11 tailq th = 64
+
+tc 12 qdelay ref = 15
+tc 12 max burst = 150
+tc 12 update interval = 15
+tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_red.cfg b/examples/qos_sched/profile_red.cfg
new file mode 100644
index 0000000000..4486d2799e
--- /dev/null
+++ b/examples/qos_sched/profile_red.cfg
@@ -0,0 +1,143 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+; RED params per traffic class and color (Green / Yellow / Red)
+[red]
+tc 0 wred min = 48 40 32
+tc 0 wred max = 64 64 64
+tc 0 wred inv prob = 10 10 10
+tc 0 wred weight = 9 9 9
+
+tc 1 wred min = 48 40 32
+tc 1 wred max = 64 64 64
+tc 1 wred inv prob = 10 10 10
+tc 1 wred weight = 9 9 9
+
+tc 2 wred min = 48 40 32
+tc 2 wred max = 64 64 64
+tc 2 wred inv prob = 10 10 10
+tc 2 wred weight = 9 9 9
+
+tc 3 wred min = 48 40 32
+tc 3 wred max = 64 64 64
+tc 3 wred inv prob = 10 10 10
+tc 3 wred weight = 9 9 9
+
+tc 4 wred min = 48 40 32
+tc 4 wred max = 64 64 64
+tc 4 wred inv prob = 10 10 10
+tc 4 wred weight = 9 9 9
+
+tc 5 wred min = 48 40 32
+tc 5 wred max = 64 64 64
+tc 5 wred inv prob = 10 10 10
+tc 5 wred weight = 9 9 9
+
+tc 6 wred min = 48 40 32
+tc 6 wred max = 64 64 64
+tc 6 wred inv prob = 10 10 10
+tc 6 wred weight = 9 9 9
+
+tc 7 wred min = 48 40 32
+tc 7 wred max = 64 64 64
+tc 7 wred inv prob = 10 10 10
+tc 7 wred weight = 9 9 9
+
+tc 8 wred min = 48 40 32
+tc 8 wred max = 64 64 64
+tc 8 wred inv prob = 10 10 10
+tc 8 wred weight = 9 9 9
+
+tc 9 wred min = 48 40 32
+tc 9 wred max = 64 64 64
+tc 9 wred inv prob = 10 10 10
+tc 9 wred weight = 9 9 9
+
+tc 10 wred min = 48 40 32
+tc 10 wred max = 64 64 64
+tc 10 wred inv prob = 10 10 10
+tc 10 wred weight = 9 9 9
+
+tc 11 wred min = 48 40 32
+tc 11 wred max = 64 64 64
+tc 11 wred inv prob = 10 10 10
+tc 11 wred weight = 9 9 9
+
+tc 12 wred min = 48 40 32
+tc 12 wred max = 64 64 64
+tc 12 wred inv prob = 10 10 10
+tc 12 wred weight = 9 9 9
diff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c
index 599c7e9536..c5fa9e4582 100644
--- a/lib/sched/rte_sched.c
+++ b/lib/sched/rte_sched.c
@@ -81,13 +81,11 @@ struct rte_sched_queue {
struct rte_sched_queue_extra {
struct rte_sched_queue_stats stats;
-#ifdef RTE_SCHED_CMAN
RTE_STD_C11
union {
struct rte_red red;
struct rte_pie pie;
};
-#endif
};
enum grinder_state {
@@ -179,7 +177,6 @@ struct rte_sched_subport {
/* Pipe queues size */
uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
-#ifdef RTE_SCHED_CMAN
bool cman_enabled;
enum rte_sched_cman_mode cman;
@@ -188,7 +185,6 @@ struct rte_sched_subport {
struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];
struct rte_pie_config pie_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
};
-#endif
/* Scheduling loop detection */
uint32_t pipe_loop;
@@ -1084,7 +1080,6 @@ rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports)
rte_free(port);
}
-#ifdef RTE_SCHED_CMAN
static int
rte_sched_red_config(struct rte_sched_port *port,
struct rte_sched_subport *s,
@@ -1166,7 +1161,6 @@ rte_sched_cman_config(struct rte_sched_port *port,
return -EINVAL;
}
-#endif
int
rte_sched_subport_tc_ov_config(struct rte_sched_port *port,
@@ -1285,7 +1279,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
/* TC oversubscription is enabled by default */
s->tc_ov_enabled = 1;
-#ifdef RTE_SCHED_CMAN
if (params->cman_params != NULL) {
s->cman_enabled = true;
status = rte_sched_cman_config(port, s, params, n_subports);
@@ -1297,7 +1290,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
} else {
s->cman_enabled = false;
}
-#endif
/* Scheduling loop detection */
s->pipe_loop = RTE_SCHED_PIPE_INVALID;
@@ -1823,7 +1815,7 @@ rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
uint32_t tc_index = rte_sched_port_pipe_tc(port, qindex);
uint32_t pkt_len = pkt->pkt_len;
@@ -1849,21 +1841,17 @@ static inline void
rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
uint32_t pkt_len = pkt->pkt_len;
qe->stats.n_pkts_dropped += 1;
qe->stats.n_bytes_dropped += pkt_len;
-#ifdef RTE_SCHED_CMAN
if (subport->cman_enabled)
qe->stats.n_pkts_cman_dropped += n_pkts_cman_dropped;
-#endif
}
-#ifdef RTE_SCHED_CMAN
-
static inline int
rte_sched_port_cman_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
@@ -1908,13 +1896,11 @@ static inline void
rte_sched_port_red_set_queue_empty_timestamp(struct rte_sched_port *port,
struct rte_sched_subport *subport, uint32_t qindex)
{
- if (subport->cman_enabled) {
+ if (subport->cman_enabled && subport->cman == RTE_SCHED_CMAN_RED) {
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
- if (subport->cman == RTE_SCHED_CMAN_RED) {
- struct rte_red *red = &qe->red;
+ struct rte_red *red = &qe->red;
- rte_red_mark_queue_empty(red, port->time);
- }
+ rte_red_mark_queue_empty(red, port->time);
}
}
@@ -1933,29 +1919,6 @@ uint32_t qindex, uint32_t pkt_len, uint64_t time) {
}
}
-#else
-
-static inline int rte_sched_port_cman_drop(struct rte_sched_port *port __rte_unused,
- struct rte_sched_subport *subport __rte_unused,
- struct rte_mbuf *pkt __rte_unused,
- uint32_t qindex __rte_unused,
- uint16_t qlen __rte_unused)
-{
- return 0;
-}
-
-#define rte_sched_port_red_set_queue_empty_timestamp(port, subport, qindex)
-
-static inline void
-rte_sched_port_pie_dequeue(struct rte_sched_subport *subport __rte_unused,
- uint32_t qindex __rte_unused,
- uint32_t pkt_len __rte_unused,
- uint64_t time __rte_unused) {
- /* do-nothing when RTE_SCHED_CMAN not defined */
-}
-
-#endif /* RTE_SCHED_CMAN */
-
#ifdef RTE_SCHED_DEBUG
static inline void
--
2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v5] ched: enable CMAN at runtime
2022-06-20 13:56 ` [PATCH v5] ched: " Marcin Danilewicz
@ 2022-06-20 14:49 ` Dumitrescu, Cristian
2022-06-21 8:20 ` Danilewicz, MarcinX
2022-06-21 8:16 ` [PATCH v6] sched: " Marcin Danilewicz
1 sibling, 1 reply; 27+ messages in thread
From: Dumitrescu, Cristian @ 2022-06-20 14:49 UTC (permalink / raw)
To: Danilewicz, MarcinX, dev, Singh, Jasvinder; +Cc: Ajmera, Megha
> -----Original Message-----
> From: Danilewicz, MarcinX <marcinx.danilewicz@intel.com>
> Sent: Monday, June 20, 2022 2:57 PM
> To: dev@dpdk.org; Singh, Jasvinder <jasvinder.singh@intel.com>;
> Dumitrescu, Cristian <cristian.dumitrescu@intel.com>
> Cc: Ajmera, Megha <megha.ajmera@intel.com>
> Subject: [PATCH v5] ched: enable CMAN at runtime
>
Title: ched -> sched
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v6] sched: enable CMAN at runtime
2022-06-20 13:56 ` [PATCH v5] ched: " Marcin Danilewicz
2022-06-20 14:49 ` Dumitrescu, Cristian
@ 2022-06-21 8:16 ` Marcin Danilewicz
2022-06-21 13:27 ` Dumitrescu, Cristian
2022-07-04 9:19 ` [PATCH v7] " Marcin Danilewicz
1 sibling, 2 replies; 27+ messages in thread
From: Marcin Danilewicz @ 2022-06-21 8:16 UTC (permalink / raw)
To: dev, jasvinder.singh, cristian.dumitrescu; +Cc: megha.ajmera
Added changes to enable CMAN (RED or PIE) at init
from profile configuration file.
By default CMAN code is enable but not in use, when
there is no RED or PIE profile configured.
Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
---
Log: v2 change in rte_sched.h to avoid ABI breakage.
v3 changes from comments
v4 rebase to 22.07-rc1
v5 rebase to main latest
v6 commit message fixed
---
config/rte_config.h | 3 -
drivers/net/softnic/rte_eth_softnic_tm.c | 12 --
examples/ip_pipeline/tmgr.c | 4 -
examples/qos_sched/cfg_file.c | 11 +-
examples/qos_sched/cfg_file.h | 2 -
examples/qos_sched/init.c | 4 -
examples/qos_sched/main.h | 2 -
examples/qos_sched/profile.cfg | 130 ++++++++++-----------
examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++
examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++
lib/sched/rte_sched.c | 47 +-------
11 files changed, 359 insertions(+), 141 deletions(-)
create mode 100644 examples/qos_sched/profile_pie.cfg
create mode 100644 examples/qos_sched/profile_red.cfg
diff --git a/config/rte_config.h b/config/rte_config.h
index 46549cb062..ae56a86394 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -88,9 +88,6 @@
/* rte_power defines */
#define RTE_MAX_LCORE_FREQS 64
-/* rte_sched defines */
-// RTE_SCHED_CMAN is not set
-
/* rte_graph defines */
#define RTE_GRAPH_BURST_SIZE 256
#define RTE_LIBRTE_GRAPH_STATS 1
diff --git a/drivers/net/softnic/rte_eth_softnic_tm.c b/drivers/net/softnic/rte_eth_softnic_tm.c
index 6a7766ba1c..3a5fd676e9 100644
--- a/drivers/net/softnic/rte_eth_softnic_tm.c
+++ b/drivers/net/softnic/rte_eth_softnic_tm.c
@@ -420,11 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,
return 0;
}
-#ifdef RTE_SCHED_CMAN
#define WRED_SUPPORTED 1
-#else
-#define WRED_SUPPORTED 0
-#endif
#define STATS_MASK_DEFAULT \
(RTE_TM_STATS_N_PKTS | \
@@ -2300,8 +2296,6 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev, uint32_t tc_id)
return NULL;
}
-#ifdef RTE_SCHED_CMAN
-
static void
wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
{
@@ -2325,12 +2319,6 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
}
}
-#else
-
-#define wred_profiles_set(dev, subport_id)
-
-#endif
-
static struct tm_shared_shaper *
tm_tc_shared_shaper_get(struct rte_eth_dev *dev, struct tm_node *tc_node)
{
diff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c
index b138e885cf..e68e9961be 100644
--- a/examples/ip_pipeline/tmgr.c
+++ b/examples/ip_pipeline/tmgr.c
@@ -17,7 +17,6 @@ static uint32_t n_subport_profiles;
static struct rte_sched_pipe_params
pipe_profile[TMGR_PIPE_PROFILE_MAX];
-#ifdef RTE_SCHED_CMAN
static struct rte_sched_cman_params cman_params = {
.red_params = {
/* Traffic Class 0 Colors Green / Yellow / Red */
@@ -86,7 +85,6 @@ static struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
static uint32_t n_pipe_profiles;
@@ -96,9 +94,7 @@ static const struct rte_sched_subport_params subport_params_default = {
.pipe_profiles = pipe_profile,
.n_pipe_profiles = 0, /* filled at run time */
.n_max_pipe_profiles = RTE_DIM(pipe_profile),
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
};
static struct tmgr_port_list tmgr_port_list;
diff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c
index 450482f07d..3284b4d252 100644
--- a/examples/qos_sched/cfg_file.c
+++ b/examples/qos_sched/cfg_file.c
@@ -229,11 +229,14 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg,
return 0;
}
-#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p)
{
int j, k;
+
+ if (subport_p->cman_params != NULL)
+ return;
+
subport_p->cman_params->cman_mode = cman_p.cman_mode;
for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
@@ -261,7 +264,6 @@ void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
}
}
}
-#endif
int
cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)
@@ -276,9 +278,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
memset(active_queues, 0, sizeof(active_queues));
n_active_queues = 0;
-#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
- .cman_mode = RTE_SCHED_CMAN_RED,
.red_params = { },
};
@@ -387,7 +387,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
-#endif /* RTE_SCHED_CMAN */
for (i = 0; i < MAX_SCHED_SUBPORTS; i++) {
char sec_name[CFG_NAME_LEN];
@@ -465,9 +464,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
}
-#ifdef RTE_SCHED_CMAN
set_subport_cman_params(subport_params+i, cman_params);
-#endif
}
}
diff --git a/examples/qos_sched/cfg_file.h b/examples/qos_sched/cfg_file.h
index 1a9dce9db5..19df91e7ba 100644
--- a/examples/qos_sched/cfg_file.h
+++ b/examples/qos_sched/cfg_file.h
@@ -12,10 +12,8 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);
int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);
-#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p);
-#endif
int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);
diff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c
index 8a0fb8a374..0afd553283 100644
--- a/examples/qos_sched/init.c
+++ b/examples/qos_sched/init.c
@@ -201,7 +201,6 @@ static struct rte_sched_subport_profile_params
},
};
-#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
.cman_mode = RTE_SCHED_CMAN_RED,
.red_params = {
@@ -271,7 +270,6 @@ struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
{
@@ -281,9 +279,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
.n_pipe_profiles = sizeof(pipe_profiles) /
sizeof(struct rte_sched_pipe_params),
.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
},
};
diff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h
index 915311bac8..76a68f585f 100644
--- a/examples/qos_sched/main.h
+++ b/examples/qos_sched/main.h
@@ -153,9 +153,7 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
extern uint32_t n_active_queues;
extern struct rte_sched_port_params port_params;
-#ifdef RTE_SCHED_CMAN
extern struct rte_sched_cman_params cman_params;
-#endif
extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];
int app_parse_args(int argc, char **argv);
diff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg
index d4b21c0170..db65b0ed01 100644
--- a/examples/qos_sched/profile.cfg
+++ b/examples/qos_sched/profile.cfg
@@ -142,68 +142,68 @@ tc 12 wrr weights = 1 1 1 1
;tc 12 wred inv prob = 10 10 10
;tc 12 wred weight = 9 9 9
-[pie]
-tc 0 qdelay ref = 15
-tc 0 max burst = 150
-tc 0 update interval = 15
-tc 0 tailq th = 64
-
-tc 1 qdelay ref = 15
-tc 1 max burst = 150
-tc 1 update interval = 15
-tc 1 tailq th = 64
-
-tc 2 qdelay ref = 15
-tc 2 max burst = 150
-tc 2 update interval = 15
-tc 2 tailq th = 64
-
-tc 3 qdelay ref = 15
-tc 3 max burst = 150
-tc 3 update interval = 15
-tc 3 tailq th = 64
-
-tc 4 qdelay ref = 15
-tc 4 max burst = 150
-tc 4 update interval = 15
-tc 4 tailq th = 64
-
-tc 5 qdelay ref = 15
-tc 5 max burst = 150
-tc 5 update interval = 15
-tc 5 tailq th = 64
-
-tc 6 qdelay ref = 15
-tc 6 max burst = 150
-tc 6 update interval = 15
-tc 6 tailq th = 64
-
-tc 7 qdelay ref = 15
-tc 7 max burst = 150
-tc 7 update interval = 15
-tc 7 tailq th = 64
-
-tc 8 qdelay ref = 15
-tc 8 max burst = 150
-tc 8 update interval = 15
-tc 8 tailq th = 64
-
-tc 9 qdelay ref = 15
-tc 9 max burst = 150
-tc 9 update interval = 15
-tc 9 tailq th = 64
-
-tc 10 qdelay ref = 15
-tc 10 max burst = 150
-tc 10 update interval = 15
-tc 10 tailq th = 64
-
-tc 11 qdelay ref = 15
-tc 11 max burst = 150
-tc 11 update interval = 15
-tc 11 tailq th = 64
-
-tc 12 qdelay ref = 15
-tc 12 max burst = 150
-tc 12 update interval = 15
-tc 12 tailq th = 64
+;[pie]
+;tc 0 qdelay ref = 15
+;tc 0 max burst = 150
+;tc 0 update interval = 15
+;tc 0 tailq th = 64
+
+;tc 1 qdelay ref = 15
+;tc 1 max burst = 150
+;tc 1 update interval = 15
+;tc 1 tailq th = 64
+
+;tc 2 qdelay ref = 15
+;tc 2 max burst = 150
+;tc 2 update interval = 15
+;tc 2 tailq th = 64
+
+;tc 3 qdelay ref = 15
+;tc 3 max burst = 150
+;tc 3 update interval = 15
+;tc 3 tailq th = 64
+
+;tc 4 qdelay ref = 15
+;tc 4 max burst = 150
+;tc 4 update interval = 15
+;tc 4 tailq th = 64
+
+;tc 5 qdelay ref = 15
+;tc 5 max burst = 150
+;tc 5 update interval = 15
+;tc 5 tailq th = 64
+
+;tc 6 qdelay ref = 15
+;tc 6 max burst = 150
+;tc 6 update interval = 15
+;tc 6 tailq th = 64
+
+;tc 7 qdelay ref = 15
+;tc 7 max burst = 150
+;tc 7 update interval = 15
+;tc 7 tailq th = 64
+
+;tc 8 qdelay ref = 15
+;tc 8 max burst = 150
+;tc 8 update interval = 15
+;tc 8 tailq th = 64
+
+;tc 9 qdelay ref = 15
+;tc 9 max burst = 150
+;tc 9 update interval = 15
+;tc 9 tailq th = 64
+
+;tc 10 qdelay ref = 15
+;tc 10 max burst = 150
+;tc 10 update interval = 15
+;tc 10 tailq th = 64
+
+;tc 11 qdelay ref = 15
+;tc 11 max burst = 150
+;tc 11 update interval = 15
+;tc 11 tailq th = 64
+
+;tc 12 qdelay ref = 15
+;tc 12 max burst = 150
+;tc 12 update interval = 15
+;tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_pie.cfg b/examples/qos_sched/profile_pie.cfg
new file mode 100644
index 0000000000..241f748b33
--- /dev/null
+++ b/examples/qos_sched/profile_pie.cfg
@@ -0,0 +1,142 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+[pie]
+tc 0 qdelay ref = 15
+tc 0 max burst = 150
+tc 0 update interval = 15
+tc 0 tailq th = 64
+
+tc 1 qdelay ref = 15
+tc 1 max burst = 150
+tc 1 update interval = 15
+tc 1 tailq th = 64
+
+tc 2 qdelay ref = 15
+tc 2 max burst = 150
+tc 2 update interval = 15
+tc 2 tailq th = 64
+
+tc 3 qdelay ref = 15
+tc 3 max burst = 150
+tc 3 update interval = 15
+tc 3 tailq th = 64
+
+tc 4 qdelay ref = 15
+tc 4 max burst = 150
+tc 4 update interval = 15
+tc 4 tailq th = 64
+
+tc 5 qdelay ref = 15
+tc 5 max burst = 150
+tc 5 update interval = 15
+tc 5 tailq th = 64
+
+tc 6 qdelay ref = 15
+tc 6 max burst = 150
+tc 6 update interval = 15
+tc 6 tailq th = 64
+
+tc 7 qdelay ref = 15
+tc 7 max burst = 150
+tc 7 update interval = 15
+tc 7 tailq th = 64
+
+tc 8 qdelay ref = 15
+tc 8 max burst = 150
+tc 8 update interval = 15
+tc 8 tailq th = 64
+
+tc 9 qdelay ref = 15
+tc 9 max burst = 150
+tc 9 update interval = 15
+tc 9 tailq th = 64
+
+tc 10 qdelay ref = 15
+tc 10 max burst = 150
+tc 10 update interval = 15
+tc 10 tailq th = 64
+
+tc 11 qdelay ref = 15
+tc 11 max burst = 150
+tc 11 update interval = 15
+tc 11 tailq th = 64
+
+tc 12 qdelay ref = 15
+tc 12 max burst = 150
+tc 12 update interval = 15
+tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_red.cfg b/examples/qos_sched/profile_red.cfg
new file mode 100644
index 0000000000..4486d2799e
--- /dev/null
+++ b/examples/qos_sched/profile_red.cfg
@@ -0,0 +1,143 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+; RED params per traffic class and color (Green / Yellow / Red)
+[red]
+tc 0 wred min = 48 40 32
+tc 0 wred max = 64 64 64
+tc 0 wred inv prob = 10 10 10
+tc 0 wred weight = 9 9 9
+
+tc 1 wred min = 48 40 32
+tc 1 wred max = 64 64 64
+tc 1 wred inv prob = 10 10 10
+tc 1 wred weight = 9 9 9
+
+tc 2 wred min = 48 40 32
+tc 2 wred max = 64 64 64
+tc 2 wred inv prob = 10 10 10
+tc 2 wred weight = 9 9 9
+
+tc 3 wred min = 48 40 32
+tc 3 wred max = 64 64 64
+tc 3 wred inv prob = 10 10 10
+tc 3 wred weight = 9 9 9
+
+tc 4 wred min = 48 40 32
+tc 4 wred max = 64 64 64
+tc 4 wred inv prob = 10 10 10
+tc 4 wred weight = 9 9 9
+
+tc 5 wred min = 48 40 32
+tc 5 wred max = 64 64 64
+tc 5 wred inv prob = 10 10 10
+tc 5 wred weight = 9 9 9
+
+tc 6 wred min = 48 40 32
+tc 6 wred max = 64 64 64
+tc 6 wred inv prob = 10 10 10
+tc 6 wred weight = 9 9 9
+
+tc 7 wred min = 48 40 32
+tc 7 wred max = 64 64 64
+tc 7 wred inv prob = 10 10 10
+tc 7 wred weight = 9 9 9
+
+tc 8 wred min = 48 40 32
+tc 8 wred max = 64 64 64
+tc 8 wred inv prob = 10 10 10
+tc 8 wred weight = 9 9 9
+
+tc 9 wred min = 48 40 32
+tc 9 wred max = 64 64 64
+tc 9 wred inv prob = 10 10 10
+tc 9 wred weight = 9 9 9
+
+tc 10 wred min = 48 40 32
+tc 10 wred max = 64 64 64
+tc 10 wred inv prob = 10 10 10
+tc 10 wred weight = 9 9 9
+
+tc 11 wred min = 48 40 32
+tc 11 wred max = 64 64 64
+tc 11 wred inv prob = 10 10 10
+tc 11 wred weight = 9 9 9
+
+tc 12 wred min = 48 40 32
+tc 12 wred max = 64 64 64
+tc 12 wred inv prob = 10 10 10
+tc 12 wred weight = 9 9 9
diff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c
index 599c7e9536..c5fa9e4582 100644
--- a/lib/sched/rte_sched.c
+++ b/lib/sched/rte_sched.c
@@ -81,13 +81,11 @@ struct rte_sched_queue {
struct rte_sched_queue_extra {
struct rte_sched_queue_stats stats;
-#ifdef RTE_SCHED_CMAN
RTE_STD_C11
union {
struct rte_red red;
struct rte_pie pie;
};
-#endif
};
enum grinder_state {
@@ -179,7 +177,6 @@ struct rte_sched_subport {
/* Pipe queues size */
uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
-#ifdef RTE_SCHED_CMAN
bool cman_enabled;
enum rte_sched_cman_mode cman;
@@ -188,7 +185,6 @@ struct rte_sched_subport {
struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];
struct rte_pie_config pie_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
};
-#endif
/* Scheduling loop detection */
uint32_t pipe_loop;
@@ -1084,7 +1080,6 @@ rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports)
rte_free(port);
}
-#ifdef RTE_SCHED_CMAN
static int
rte_sched_red_config(struct rte_sched_port *port,
struct rte_sched_subport *s,
@@ -1166,7 +1161,6 @@ rte_sched_cman_config(struct rte_sched_port *port,
return -EINVAL;
}
-#endif
int
rte_sched_subport_tc_ov_config(struct rte_sched_port *port,
@@ -1285,7 +1279,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
/* TC oversubscription is enabled by default */
s->tc_ov_enabled = 1;
-#ifdef RTE_SCHED_CMAN
if (params->cman_params != NULL) {
s->cman_enabled = true;
status = rte_sched_cman_config(port, s, params, n_subports);
@@ -1297,7 +1290,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
} else {
s->cman_enabled = false;
}
-#endif
/* Scheduling loop detection */
s->pipe_loop = RTE_SCHED_PIPE_INVALID;
@@ -1823,7 +1815,7 @@ rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
uint32_t tc_index = rte_sched_port_pipe_tc(port, qindex);
uint32_t pkt_len = pkt->pkt_len;
@@ -1849,21 +1841,17 @@ static inline void
rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
uint32_t pkt_len = pkt->pkt_len;
qe->stats.n_pkts_dropped += 1;
qe->stats.n_bytes_dropped += pkt_len;
-#ifdef RTE_SCHED_CMAN
if (subport->cman_enabled)
qe->stats.n_pkts_cman_dropped += n_pkts_cman_dropped;
-#endif
}
-#ifdef RTE_SCHED_CMAN
-
static inline int
rte_sched_port_cman_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
@@ -1908,13 +1896,11 @@ static inline void
rte_sched_port_red_set_queue_empty_timestamp(struct rte_sched_port *port,
struct rte_sched_subport *subport, uint32_t qindex)
{
- if (subport->cman_enabled) {
+ if (subport->cman_enabled && subport->cman == RTE_SCHED_CMAN_RED) {
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
- if (subport->cman == RTE_SCHED_CMAN_RED) {
- struct rte_red *red = &qe->red;
+ struct rte_red *red = &qe->red;
- rte_red_mark_queue_empty(red, port->time);
- }
+ rte_red_mark_queue_empty(red, port->time);
}
}
@@ -1933,29 +1919,6 @@ uint32_t qindex, uint32_t pkt_len, uint64_t time) {
}
}
-#else
-
-static inline int rte_sched_port_cman_drop(struct rte_sched_port *port __rte_unused,
- struct rte_sched_subport *subport __rte_unused,
- struct rte_mbuf *pkt __rte_unused,
- uint32_t qindex __rte_unused,
- uint16_t qlen __rte_unused)
-{
- return 0;
-}
-
-#define rte_sched_port_red_set_queue_empty_timestamp(port, subport, qindex)
-
-static inline void
-rte_sched_port_pie_dequeue(struct rte_sched_subport *subport __rte_unused,
- uint32_t qindex __rte_unused,
- uint32_t pkt_len __rte_unused,
- uint64_t time __rte_unused) {
- /* do-nothing when RTE_SCHED_CMAN not defined */
-}
-
-#endif /* RTE_SCHED_CMAN */
-
#ifdef RTE_SCHED_DEBUG
static inline void
--
2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v5] ched: enable CMAN at runtime
2022-06-20 14:49 ` Dumitrescu, Cristian
@ 2022-06-21 8:20 ` Danilewicz, MarcinX
0 siblings, 0 replies; 27+ messages in thread
From: Danilewicz, MarcinX @ 2022-06-21 8:20 UTC (permalink / raw)
To: Dumitrescu, Cristian, dev, Singh, Jasvinder; +Cc: Ajmera, Megha
<snip>
> > Subject: [PATCH v5] ched: enable CMAN at runtime
> >
>
> Title: ched -> sched
Indeed!
BR,
/Marcin
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v6] sched: enable CMAN at runtime
2022-06-21 8:16 ` [PATCH v6] sched: " Marcin Danilewicz
@ 2022-06-21 13:27 ` Dumitrescu, Cristian
2022-06-22 15:12 ` Danilewicz, MarcinX
2022-07-04 9:19 ` [PATCH v7] " Marcin Danilewicz
1 sibling, 1 reply; 27+ messages in thread
From: Dumitrescu, Cristian @ 2022-06-21 13:27 UTC (permalink / raw)
To: Danilewicz, MarcinX, dev, Singh, Jasvinder; +Cc: Ajmera, Megha, Liu, Yu Y
Hi Marcin,
The code changes in the library (rte-sched.c) look good to me, but I do have some questions for the qos_sched app and the Soft NIC driver on how CMAN gets enabled/disabled.
How do we control whether congestion management (CMAN) should be disabled on enabled (WRED/PIE)? It looks to me like you are always enabling WRED by default, which is incorrect: we should have CMAN disabled by default (in init.c).
My preferred way to configure CMAN is:
a) CMAN should be disabled by default
b) If the CMAN parameters get configured in the profile.cfg, then and only then CMAN should be enabled according to the configuration.
In init.c, we can safely set the subport CMAN parameters to NULL as the built-in default when the profile.cfg is not provided, so we can safely remove the WRED params from there.
In cfg_file.c, we need to have a good way to disable/enable CMAN.
In profile.cfg, please remove the WRED lines as opposed to commenting them out.
Is this OK with you?
Also, have you tested the qos_sched app and the Soft NIC driver with all 3 configuration files?
Thanks,
Cristian
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v6] sched: enable CMAN at runtime
2022-06-21 13:27 ` Dumitrescu, Cristian
@ 2022-06-22 15:12 ` Danilewicz, MarcinX
0 siblings, 0 replies; 27+ messages in thread
From: Danilewicz, MarcinX @ 2022-06-22 15:12 UTC (permalink / raw)
To: Dumitrescu, Cristian, dev, Singh, Jasvinder; +Cc: Ajmera, Megha, Liu, Yu Y
Hi Cristian,
<SNIP>
> The code changes in the library (rte-sched.c) look good to me, but I do have
> some questions for the qos_sched app and the Soft NIC driver on how CMAN
> gets enabled/disabled.
That was open q from start. We finally found a time to discuss this.
> How do we control whether congestion management (CMAN) should be
> disabled on enabled (WRED/PIE)? It looks to me like you are always enabling
> WRED by default, which is incorrect: we should have CMAN disabled by
> default (in init.c).
Cannot disagree.
> My preferred way to configure CMAN is:
> a) CMAN should be disabled by default
> b) If the CMAN parameters get configured in the profile.cfg, then and only
> then CMAN should be enabled according to the configuration.
OK
> In init.c, we can safely set the subport CMAN parameters to NULL as the
> built-in default when the profile.cfg is not provided, so we can safely remove
> the WRED params from there.
Agree
> In cfg_file.c, we need to have a good way to disable/enable CMAN.
Let me provide something and then you will have a look at it.
> In profile.cfg, please remove the WRED lines as opposed to commenting
> them out.
OK
> Is this OK with you?
That's perfectly fine and looks good.
> Also, have you tested the qos_sched app and the Soft NIC driver with all 3
> configuration files?
Obviously yes, but not the last time. And I will repeat such testing as the last thing.
Kind Regards,
/Marcin
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v7] sched: enable CMAN at runtime
2022-06-21 8:16 ` [PATCH v6] sched: " Marcin Danilewicz
2022-06-21 13:27 ` Dumitrescu, Cristian
@ 2022-07-04 9:19 ` Marcin Danilewicz
2022-07-05 17:05 ` [PATCH v8] " Marcin Danilewicz
1 sibling, 1 reply; 27+ messages in thread
From: Marcin Danilewicz @ 2022-07-04 9:19 UTC (permalink / raw)
To: dev, jasvinder.singh, cristian.dumitrescu; +Cc: megha.ajmera
Added changes to enable CMAN (RED or PIE) at init
from profile configuration file.
By default CMAN code is enable but not in use, when
there is no RED or PIE profile configured.
Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
---
Log: v2 change in rte_sched.h to avoid ABI breakage.
v3 changes from comments
v4 rebase to 22.07-rc1
v5 rebase to main latest
v6 commit message fixed
v7 changes from comments
---
config/rte_config.h | 3 -
drivers/net/softnic/rte_eth_softnic_tm.c | 12 --
examples/ip_pipeline/tmgr.c | 4 -
examples/qos_sched/cfg_file.c | 11 +-
examples/qos_sched/cfg_file.h | 2 -
examples/qos_sched/init.c | 4 -
examples/qos_sched/main.h | 2 -
examples/qos_sched/profile.cfg | 135 +--------------------
examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++
examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++
lib/sched/rte_sched.c | 47 +-------
11 files changed, 295 insertions(+), 210 deletions(-)
create mode 100644 examples/qos_sched/profile_pie.cfg
create mode 100644 examples/qos_sched/profile_red.cfg
diff --git a/config/rte_config.h b/config/rte_config.h
index 46549cb062..ae56a86394 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -88,9 +88,6 @@
/* rte_power defines */
#define RTE_MAX_LCORE_FREQS 64
-/* rte_sched defines */
-// RTE_SCHED_CMAN is not set
-
/* rte_graph defines */
#define RTE_GRAPH_BURST_SIZE 256
#define RTE_LIBRTE_GRAPH_STATS 1
diff --git a/drivers/net/softnic/rte_eth_softnic_tm.c b/drivers/net/softnic/rte_eth_softnic_tm.c
index 6a7766ba1c..3e4bed81e9 100644
--- a/drivers/net/softnic/rte_eth_softnic_tm.c
+++ b/drivers/net/softnic/rte_eth_softnic_tm.c
@@ -420,11 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,
return 0;
}
-#ifdef RTE_SCHED_CMAN
-#define WRED_SUPPORTED 1
-#else
#define WRED_SUPPORTED 0
-#endif
#define STATS_MASK_DEFAULT \
(RTE_TM_STATS_N_PKTS | \
@@ -2300,8 +2296,6 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev, uint32_t tc_id)
return NULL;
}
-#ifdef RTE_SCHED_CMAN
-
static void
wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
{
@@ -2325,12 +2319,6 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
}
}
-#else
-
-#define wred_profiles_set(dev, subport_id)
-
-#endif
-
static struct tm_shared_shaper *
tm_tc_shared_shaper_get(struct rte_eth_dev *dev, struct tm_node *tc_node)
{
diff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c
index b138e885cf..e68e9961be 100644
--- a/examples/ip_pipeline/tmgr.c
+++ b/examples/ip_pipeline/tmgr.c
@@ -17,7 +17,6 @@ static uint32_t n_subport_profiles;
static struct rte_sched_pipe_params
pipe_profile[TMGR_PIPE_PROFILE_MAX];
-#ifdef RTE_SCHED_CMAN
static struct rte_sched_cman_params cman_params = {
.red_params = {
/* Traffic Class 0 Colors Green / Yellow / Red */
@@ -86,7 +85,6 @@ static struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
static uint32_t n_pipe_profiles;
@@ -96,9 +94,7 @@ static const struct rte_sched_subport_params subport_params_default = {
.pipe_profiles = pipe_profile,
.n_pipe_profiles = 0, /* filled at run time */
.n_max_pipe_profiles = RTE_DIM(pipe_profile),
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
};
static struct tmgr_port_list tmgr_port_list;
diff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c
index 450482f07d..3284b4d252 100644
--- a/examples/qos_sched/cfg_file.c
+++ b/examples/qos_sched/cfg_file.c
@@ -229,11 +229,14 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg,
return 0;
}
-#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p)
{
int j, k;
+
+ if (subport_p->cman_params != NULL)
+ return;
+
subport_p->cman_params->cman_mode = cman_p.cman_mode;
for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
@@ -261,7 +264,6 @@ void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
}
}
}
-#endif
int
cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)
@@ -276,9 +278,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
memset(active_queues, 0, sizeof(active_queues));
n_active_queues = 0;
-#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
- .cman_mode = RTE_SCHED_CMAN_RED,
.red_params = { },
};
@@ -387,7 +387,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
-#endif /* RTE_SCHED_CMAN */
for (i = 0; i < MAX_SCHED_SUBPORTS; i++) {
char sec_name[CFG_NAME_LEN];
@@ -465,9 +464,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
}
-#ifdef RTE_SCHED_CMAN
set_subport_cman_params(subport_params+i, cman_params);
-#endif
}
}
diff --git a/examples/qos_sched/cfg_file.h b/examples/qos_sched/cfg_file.h
index 1a9dce9db5..19df91e7ba 100644
--- a/examples/qos_sched/cfg_file.h
+++ b/examples/qos_sched/cfg_file.h
@@ -12,10 +12,8 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);
int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);
-#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p);
-#endif
int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);
diff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c
index 8a0fb8a374..0afd553283 100644
--- a/examples/qos_sched/init.c
+++ b/examples/qos_sched/init.c
@@ -201,7 +201,6 @@ static struct rte_sched_subport_profile_params
},
};
-#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
.cman_mode = RTE_SCHED_CMAN_RED,
.red_params = {
@@ -271,7 +270,6 @@ struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
{
@@ -281,9 +279,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
.n_pipe_profiles = sizeof(pipe_profiles) /
sizeof(struct rte_sched_pipe_params),
.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
},
};
diff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h
index 915311bac8..76a68f585f 100644
--- a/examples/qos_sched/main.h
+++ b/examples/qos_sched/main.h
@@ -153,9 +153,7 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
extern uint32_t n_active_queues;
extern struct rte_sched_port_params port_params;
-#ifdef RTE_SCHED_CMAN
extern struct rte_sched_cman_params cman_params;
-#endif
extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];
int app_parse_args(int argc, char **argv);
diff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg
index d4b21c0170..c9ec187c93 100644
--- a/examples/qos_sched/profile.cfg
+++ b/examples/qos_sched/profile.cfg
@@ -73,137 +73,4 @@ tc period = 40 ; Milliseconds
tc 12 oversubscription weight = 1
-tc 12 wrr weights = 1 1 1 1
-
-; RED params per traffic class and color (Green / Yellow / Red)
-;[red]
-;tc 0 wred min = 48 40 32
-;tc 0 wred max = 64 64 64
-;tc 0 wred inv prob = 10 10 10
-;tc 0 wred weight = 9 9 9
-
-;tc 1 wred min = 48 40 32
-;tc 1 wred max = 64 64 64
-;tc 1 wred inv prob = 10 10 10
-;tc 1 wred weight = 9 9 9
-
-;tc 2 wred min = 48 40 32
-;tc 2 wred max = 64 64 64
-;tc 2 wred inv prob = 10 10 10
-;tc 2 wred weight = 9 9 9
-
-;tc 3 wred min = 48 40 32
-;tc 3 wred max = 64 64 64
-;tc 3 wred inv prob = 10 10 10
-;tc 3 wred weight = 9 9 9
-
-;tc 4 wred min = 48 40 32
-;tc 4 wred max = 64 64 64
-;tc 4 wred inv prob = 10 10 10
-;tc 4 wred weight = 9 9 9
-
-;tc 5 wred min = 48 40 32
-;tc 5 wred max = 64 64 64
-;tc 5 wred inv prob = 10 10 10
-;tc 5 wred weight = 9 9 9
-
-;tc 6 wred min = 48 40 32
-;tc 6 wred max = 64 64 64
-;tc 6 wred inv prob = 10 10 10
-;tc 6 wred weight = 9 9 9
-
-;tc 7 wred min = 48 40 32
-;tc 7 wred max = 64 64 64
-;tc 7 wred inv prob = 10 10 10
-;tc 7 wred weight = 9 9 9
-
-;tc 8 wred min = 48 40 32
-;tc 8 wred max = 64 64 64
-;tc 8 wred inv prob = 10 10 10
-;tc 8 wred weight = 9 9 9
-
-;tc 9 wred min = 48 40 32
-;tc 9 wred max = 64 64 64
-;tc 9 wred inv prob = 10 10 10
-;tc 9 wred weight = 9 9 9
-
-;tc 10 wred min = 48 40 32
-;tc 10 wred max = 64 64 64
-;tc 10 wred inv prob = 10 10 10
-;tc 10 wred weight = 9 9 9
-
-;tc 11 wred min = 48 40 32
-;tc 11 wred max = 64 64 64
-;tc 11 wred inv prob = 10 10 10
-;tc 11 wred weight = 9 9 9
-
-;tc 12 wred min = 48 40 32
-;tc 12 wred max = 64 64 64
-;tc 12 wred inv prob = 10 10 10
-;tc 12 wred weight = 9 9 9
-
-[pie]
-tc 0 qdelay ref = 15
-tc 0 max burst = 150
-tc 0 update interval = 15
-tc 0 tailq th = 64
-
-tc 1 qdelay ref = 15
-tc 1 max burst = 150
-tc 1 update interval = 15
-tc 1 tailq th = 64
-
-tc 2 qdelay ref = 15
-tc 2 max burst = 150
-tc 2 update interval = 15
-tc 2 tailq th = 64
-
-tc 3 qdelay ref = 15
-tc 3 max burst = 150
-tc 3 update interval = 15
-tc 3 tailq th = 64
-
-tc 4 qdelay ref = 15
-tc 4 max burst = 150
-tc 4 update interval = 15
-tc 4 tailq th = 64
-
-tc 5 qdelay ref = 15
-tc 5 max burst = 150
-tc 5 update interval = 15
-tc 5 tailq th = 64
-
-tc 6 qdelay ref = 15
-tc 6 max burst = 150
-tc 6 update interval = 15
-tc 6 tailq th = 64
-
-tc 7 qdelay ref = 15
-tc 7 max burst = 150
-tc 7 update interval = 15
-tc 7 tailq th = 64
-
-tc 8 qdelay ref = 15
-tc 8 max burst = 150
-tc 8 update interval = 15
-tc 8 tailq th = 64
-
-tc 9 qdelay ref = 15
-tc 9 max burst = 150
-tc 9 update interval = 15
-tc 9 tailq th = 64
-
-tc 10 qdelay ref = 15
-tc 10 max burst = 150
-tc 10 update interval = 15
-tc 10 tailq th = 64
-
-tc 11 qdelay ref = 15
-tc 11 max burst = 150
-tc 11 update interval = 15
-tc 11 tailq th = 64
-
-tc 12 qdelay ref = 15
-tc 12 max burst = 150
-tc 12 update interval = 15
-tc 12 tailq th = 64
+tc 12 wrr weights = 1 1 1 1
\ No newline at end of file
diff --git a/examples/qos_sched/profile_pie.cfg b/examples/qos_sched/profile_pie.cfg
new file mode 100644
index 0000000000..241f748b33
--- /dev/null
+++ b/examples/qos_sched/profile_pie.cfg
@@ -0,0 +1,142 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+[pie]
+tc 0 qdelay ref = 15
+tc 0 max burst = 150
+tc 0 update interval = 15
+tc 0 tailq th = 64
+
+tc 1 qdelay ref = 15
+tc 1 max burst = 150
+tc 1 update interval = 15
+tc 1 tailq th = 64
+
+tc 2 qdelay ref = 15
+tc 2 max burst = 150
+tc 2 update interval = 15
+tc 2 tailq th = 64
+
+tc 3 qdelay ref = 15
+tc 3 max burst = 150
+tc 3 update interval = 15
+tc 3 tailq th = 64
+
+tc 4 qdelay ref = 15
+tc 4 max burst = 150
+tc 4 update interval = 15
+tc 4 tailq th = 64
+
+tc 5 qdelay ref = 15
+tc 5 max burst = 150
+tc 5 update interval = 15
+tc 5 tailq th = 64
+
+tc 6 qdelay ref = 15
+tc 6 max burst = 150
+tc 6 update interval = 15
+tc 6 tailq th = 64
+
+tc 7 qdelay ref = 15
+tc 7 max burst = 150
+tc 7 update interval = 15
+tc 7 tailq th = 64
+
+tc 8 qdelay ref = 15
+tc 8 max burst = 150
+tc 8 update interval = 15
+tc 8 tailq th = 64
+
+tc 9 qdelay ref = 15
+tc 9 max burst = 150
+tc 9 update interval = 15
+tc 9 tailq th = 64
+
+tc 10 qdelay ref = 15
+tc 10 max burst = 150
+tc 10 update interval = 15
+tc 10 tailq th = 64
+
+tc 11 qdelay ref = 15
+tc 11 max burst = 150
+tc 11 update interval = 15
+tc 11 tailq th = 64
+
+tc 12 qdelay ref = 15
+tc 12 max burst = 150
+tc 12 update interval = 15
+tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_red.cfg b/examples/qos_sched/profile_red.cfg
new file mode 100644
index 0000000000..4486d2799e
--- /dev/null
+++ b/examples/qos_sched/profile_red.cfg
@@ -0,0 +1,143 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+; RED params per traffic class and color (Green / Yellow / Red)
+[red]
+tc 0 wred min = 48 40 32
+tc 0 wred max = 64 64 64
+tc 0 wred inv prob = 10 10 10
+tc 0 wred weight = 9 9 9
+
+tc 1 wred min = 48 40 32
+tc 1 wred max = 64 64 64
+tc 1 wred inv prob = 10 10 10
+tc 1 wred weight = 9 9 9
+
+tc 2 wred min = 48 40 32
+tc 2 wred max = 64 64 64
+tc 2 wred inv prob = 10 10 10
+tc 2 wred weight = 9 9 9
+
+tc 3 wred min = 48 40 32
+tc 3 wred max = 64 64 64
+tc 3 wred inv prob = 10 10 10
+tc 3 wred weight = 9 9 9
+
+tc 4 wred min = 48 40 32
+tc 4 wred max = 64 64 64
+tc 4 wred inv prob = 10 10 10
+tc 4 wred weight = 9 9 9
+
+tc 5 wred min = 48 40 32
+tc 5 wred max = 64 64 64
+tc 5 wred inv prob = 10 10 10
+tc 5 wred weight = 9 9 9
+
+tc 6 wred min = 48 40 32
+tc 6 wred max = 64 64 64
+tc 6 wred inv prob = 10 10 10
+tc 6 wred weight = 9 9 9
+
+tc 7 wred min = 48 40 32
+tc 7 wred max = 64 64 64
+tc 7 wred inv prob = 10 10 10
+tc 7 wred weight = 9 9 9
+
+tc 8 wred min = 48 40 32
+tc 8 wred max = 64 64 64
+tc 8 wred inv prob = 10 10 10
+tc 8 wred weight = 9 9 9
+
+tc 9 wred min = 48 40 32
+tc 9 wred max = 64 64 64
+tc 9 wred inv prob = 10 10 10
+tc 9 wred weight = 9 9 9
+
+tc 10 wred min = 48 40 32
+tc 10 wred max = 64 64 64
+tc 10 wred inv prob = 10 10 10
+tc 10 wred weight = 9 9 9
+
+tc 11 wred min = 48 40 32
+tc 11 wred max = 64 64 64
+tc 11 wred inv prob = 10 10 10
+tc 11 wred weight = 9 9 9
+
+tc 12 wred min = 48 40 32
+tc 12 wred max = 64 64 64
+tc 12 wred inv prob = 10 10 10
+tc 12 wred weight = 9 9 9
diff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c
index 599c7e9536..c5fa9e4582 100644
--- a/lib/sched/rte_sched.c
+++ b/lib/sched/rte_sched.c
@@ -81,13 +81,11 @@ struct rte_sched_queue {
struct rte_sched_queue_extra {
struct rte_sched_queue_stats stats;
-#ifdef RTE_SCHED_CMAN
RTE_STD_C11
union {
struct rte_red red;
struct rte_pie pie;
};
-#endif
};
enum grinder_state {
@@ -179,7 +177,6 @@ struct rte_sched_subport {
/* Pipe queues size */
uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
-#ifdef RTE_SCHED_CMAN
bool cman_enabled;
enum rte_sched_cman_mode cman;
@@ -188,7 +185,6 @@ struct rte_sched_subport {
struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];
struct rte_pie_config pie_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
};
-#endif
/* Scheduling loop detection */
uint32_t pipe_loop;
@@ -1084,7 +1080,6 @@ rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports)
rte_free(port);
}
-#ifdef RTE_SCHED_CMAN
static int
rte_sched_red_config(struct rte_sched_port *port,
struct rte_sched_subport *s,
@@ -1166,7 +1161,6 @@ rte_sched_cman_config(struct rte_sched_port *port,
return -EINVAL;
}
-#endif
int
rte_sched_subport_tc_ov_config(struct rte_sched_port *port,
@@ -1285,7 +1279,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
/* TC oversubscription is enabled by default */
s->tc_ov_enabled = 1;
-#ifdef RTE_SCHED_CMAN
if (params->cman_params != NULL) {
s->cman_enabled = true;
status = rte_sched_cman_config(port, s, params, n_subports);
@@ -1297,7 +1290,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
} else {
s->cman_enabled = false;
}
-#endif
/* Scheduling loop detection */
s->pipe_loop = RTE_SCHED_PIPE_INVALID;
@@ -1823,7 +1815,7 @@ rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
uint32_t tc_index = rte_sched_port_pipe_tc(port, qindex);
uint32_t pkt_len = pkt->pkt_len;
@@ -1849,21 +1841,17 @@ static inline void
rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
uint32_t pkt_len = pkt->pkt_len;
qe->stats.n_pkts_dropped += 1;
qe->stats.n_bytes_dropped += pkt_len;
-#ifdef RTE_SCHED_CMAN
if (subport->cman_enabled)
qe->stats.n_pkts_cman_dropped += n_pkts_cman_dropped;
-#endif
}
-#ifdef RTE_SCHED_CMAN
-
static inline int
rte_sched_port_cman_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
@@ -1908,13 +1896,11 @@ static inline void
rte_sched_port_red_set_queue_empty_timestamp(struct rte_sched_port *port,
struct rte_sched_subport *subport, uint32_t qindex)
{
- if (subport->cman_enabled) {
+ if (subport->cman_enabled && subport->cman == RTE_SCHED_CMAN_RED) {
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
- if (subport->cman == RTE_SCHED_CMAN_RED) {
- struct rte_red *red = &qe->red;
+ struct rte_red *red = &qe->red;
- rte_red_mark_queue_empty(red, port->time);
- }
+ rte_red_mark_queue_empty(red, port->time);
}
}
@@ -1933,29 +1919,6 @@ uint32_t qindex, uint32_t pkt_len, uint64_t time) {
}
}
-#else
-
-static inline int rte_sched_port_cman_drop(struct rte_sched_port *port __rte_unused,
- struct rte_sched_subport *subport __rte_unused,
- struct rte_mbuf *pkt __rte_unused,
- uint32_t qindex __rte_unused,
- uint16_t qlen __rte_unused)
-{
- return 0;
-}
-
-#define rte_sched_port_red_set_queue_empty_timestamp(port, subport, qindex)
-
-static inline void
-rte_sched_port_pie_dequeue(struct rte_sched_subport *subport __rte_unused,
- uint32_t qindex __rte_unused,
- uint32_t pkt_len __rte_unused,
- uint64_t time __rte_unused) {
- /* do-nothing when RTE_SCHED_CMAN not defined */
-}
-
-#endif /* RTE_SCHED_CMAN */
-
#ifdef RTE_SCHED_DEBUG
static inline void
--
2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v8] sched: enable CMAN at runtime
2022-07-04 9:19 ` [PATCH v7] " Marcin Danilewicz
@ 2022-07-05 17:05 ` Marcin Danilewicz
2022-07-05 18:00 ` Ajmera, Megha
` (2 more replies)
0 siblings, 3 replies; 27+ messages in thread
From: Marcin Danilewicz @ 2022-07-05 17:05 UTC (permalink / raw)
To: dev, jasvinder.singh, cristian.dumitrescu; +Cc: megha.ajmera
Added changes to enable CMAN (RED or PIE) at init
from profile configuration file.
By default CMAN code is enable but not in use, when
there is no RED or PIE profile configured.
Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
---
Log: v2 change in rte_sched.h to avoid ABI breakage.
v3 changes from comments
v4 rebase to 22.07-rc1
v5 rebase to main latest
v6 commit message fixed
v7 changes from comments
v8 with changes from comments
---
config/rte_config.h | 3 -
drivers/net/softnic/rte_eth_softnic_tm.c | 12 --
examples/ip_pipeline/tmgr.c | 4 -
examples/qos_sched/cfg_file.c | 47 +-------
examples/qos_sched/cfg_file.h | 5 -
examples/qos_sched/init.c | 76 +-----------
examples/qos_sched/main.h | 2 -
examples/qos_sched/profile.cfg | 135 +--------------------
examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++
examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++
lib/sched/rte_sched.c | 47 +-------
11 files changed, 296 insertions(+), 320 deletions(-)
create mode 100644 examples/qos_sched/profile_pie.cfg
create mode 100644 examples/qos_sched/profile_red.cfg
diff --git a/config/rte_config.h b/config/rte_config.h
index 46549cb062..ae56a86394 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -88,9 +88,6 @@
/* rte_power defines */
#define RTE_MAX_LCORE_FREQS 64
-/* rte_sched defines */
-// RTE_SCHED_CMAN is not set
-
/* rte_graph defines */
#define RTE_GRAPH_BURST_SIZE 256
#define RTE_LIBRTE_GRAPH_STATS 1
diff --git a/drivers/net/softnic/rte_eth_softnic_tm.c b/drivers/net/softnic/rte_eth_softnic_tm.c
index 6a7766ba1c..3e4bed81e9 100644
--- a/drivers/net/softnic/rte_eth_softnic_tm.c
+++ b/drivers/net/softnic/rte_eth_softnic_tm.c
@@ -420,11 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,
return 0;
}
-#ifdef RTE_SCHED_CMAN
-#define WRED_SUPPORTED 1
-#else
#define WRED_SUPPORTED 0
-#endif
#define STATS_MASK_DEFAULT \
(RTE_TM_STATS_N_PKTS | \
@@ -2300,8 +2296,6 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev, uint32_t tc_id)
return NULL;
}
-#ifdef RTE_SCHED_CMAN
-
static void
wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
{
@@ -2325,12 +2319,6 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
}
}
-#else
-
-#define wred_profiles_set(dev, subport_id)
-
-#endif
-
static struct tm_shared_shaper *
tm_tc_shared_shaper_get(struct rte_eth_dev *dev, struct tm_node *tc_node)
{
diff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c
index b138e885cf..e68e9961be 100644
--- a/examples/ip_pipeline/tmgr.c
+++ b/examples/ip_pipeline/tmgr.c
@@ -17,7 +17,6 @@ static uint32_t n_subport_profiles;
static struct rte_sched_pipe_params
pipe_profile[TMGR_PIPE_PROFILE_MAX];
-#ifdef RTE_SCHED_CMAN
static struct rte_sched_cman_params cman_params = {
.red_params = {
/* Traffic Class 0 Colors Green / Yellow / Red */
@@ -86,7 +85,6 @@ static struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
static uint32_t n_pipe_profiles;
@@ -96,9 +94,7 @@ static const struct rte_sched_subport_params subport_params_default = {
.pipe_profiles = pipe_profile,
.n_pipe_profiles = 0, /* filled at run time */
.n_max_pipe_profiles = RTE_DIM(pipe_profile),
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
};
static struct tmgr_port_list tmgr_port_list;
diff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c
index 450482f07d..7f4114bd56 100644
--- a/examples/qos_sched/cfg_file.c
+++ b/examples/qos_sched/cfg_file.c
@@ -23,6 +23,8 @@
uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
uint32_t n_active_queues;
+struct rte_sched_cman_params cman_params;
+
int
cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port_params)
{
@@ -229,40 +231,6 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg,
return 0;
}
-#ifdef RTE_SCHED_CMAN
-void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
- struct rte_sched_cman_params cman_p)
-{
- int j, k;
- subport_p->cman_params->cman_mode = cman_p.cman_mode;
-
- for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
- if (subport_p->cman_params->cman_mode ==
- RTE_SCHED_CMAN_RED) {
- for (k = 0; k < RTE_COLORS; k++) {
- subport_p->cman_params->red_params[j][k].min_th =
- cman_p.red_params[j][k].min_th;
- subport_p->cman_params->red_params[j][k].max_th =
- cman_p.red_params[j][k].max_th;
- subport_p->cman_params->red_params[j][k].maxp_inv =
- cman_p.red_params[j][k].maxp_inv;
- subport_p->cman_params->red_params[j][k].wq_log2 =
- cman_p.red_params[j][k].wq_log2;
- }
- } else {
- subport_p->cman_params->pie_params[j].qdelay_ref =
- cman_p.pie_params[j].qdelay_ref;
- subport_p->cman_params->pie_params[j].dp_update_interval =
- cman_p.pie_params[j].dp_update_interval;
- subport_p->cman_params->pie_params[j].max_burst =
- cman_p.pie_params[j].max_burst;
- subport_p->cman_params->pie_params[j].tailq_th =
- cman_p.pie_params[j].tailq_th;
- }
- }
-}
-#endif
-
int
cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)
{
@@ -276,11 +244,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
memset(active_queues, 0, sizeof(active_queues));
n_active_queues = 0;
-#ifdef RTE_SCHED_CMAN
- struct rte_sched_cman_params cman_params = {
- .cman_mode = RTE_SCHED_CMAN_RED,
- .red_params = { },
- };
+ subport_params->cman_params = NULL;
if (rte_cfgfile_has_section(cfg, "red")) {
cman_params.cman_mode = RTE_SCHED_CMAN_RED;
@@ -387,7 +351,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
-#endif /* RTE_SCHED_CMAN */
for (i = 0; i < MAX_SCHED_SUBPORTS; i++) {
char sec_name[CFG_NAME_LEN];
@@ -465,9 +428,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
}
-#ifdef RTE_SCHED_CMAN
- set_subport_cman_params(subport_params+i, cman_params);
-#endif
+ subport_params[i].cman_params = &cman_params;
}
}
diff --git a/examples/qos_sched/cfg_file.h b/examples/qos_sched/cfg_file.h
index 1a9dce9db5..0dc458aa71 100644
--- a/examples/qos_sched/cfg_file.h
+++ b/examples/qos_sched/cfg_file.h
@@ -12,11 +12,6 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);
int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);
-#ifdef RTE_SCHED_CMAN
-void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
- struct rte_sched_cman_params cman_p);
-#endif
-
int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);
int cfg_load_subport_profile(struct rte_cfgfile *cfg,
diff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c
index 8a0fb8a374..e8b819ffb9 100644
--- a/examples/qos_sched/init.c
+++ b/examples/qos_sched/init.c
@@ -201,78 +201,6 @@ static struct rte_sched_subport_profile_params
},
};
-#ifdef RTE_SCHED_CMAN
-struct rte_sched_cman_params cman_params = {
- .cman_mode = RTE_SCHED_CMAN_RED,
- .red_params = {
- /* Traffic Class 0 Colors Green / Yellow / Red */
- [0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 1 - Colors Green / Yellow / Red */
- [1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 2 - Colors Green / Yellow / Red */
- [2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 3 - Colors Green / Yellow / Red */
- [3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 4 - Colors Green / Yellow / Red */
- [4][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [4][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [4][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 5 - Colors Green / Yellow / Red */
- [5][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [5][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [5][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 6 - Colors Green / Yellow / Red */
- [6][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [6][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [6][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 7 - Colors Green / Yellow / Red */
- [7][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [7][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [7][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 8 - Colors Green / Yellow / Red */
- [8][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [8][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [8][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 9 - Colors Green / Yellow / Red */
- [9][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [9][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [9][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 10 - Colors Green / Yellow / Red */
- [10][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [10][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [10][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 11 - Colors Green / Yellow / Red */
- [11][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [11][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [11][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 12 - Colors Green / Yellow / Red */
- [12][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- },
-};
-#endif /* RTE_SCHED_CMAN */
-
struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
{
.n_pipes_per_subport_enabled = 4096,
@@ -281,9 +209,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
.n_pipe_profiles = sizeof(pipe_profiles) /
sizeof(struct rte_sched_pipe_params),
.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,
-#ifdef RTE_SCHED_CMAN
- .cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
+ .cman_params = NULL,
},
};
diff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h
index 915311bac8..76a68f585f 100644
--- a/examples/qos_sched/main.h
+++ b/examples/qos_sched/main.h
@@ -153,9 +153,7 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
extern uint32_t n_active_queues;
extern struct rte_sched_port_params port_params;
-#ifdef RTE_SCHED_CMAN
extern struct rte_sched_cman_params cman_params;
-#endif
extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];
int app_parse_args(int argc, char **argv);
diff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg
index d4b21c0170..c9ec187c93 100644
--- a/examples/qos_sched/profile.cfg
+++ b/examples/qos_sched/profile.cfg
@@ -73,137 +73,4 @@ tc period = 40 ; Milliseconds
tc 12 oversubscription weight = 1
-tc 12 wrr weights = 1 1 1 1
-
-; RED params per traffic class and color (Green / Yellow / Red)
-;[red]
-;tc 0 wred min = 48 40 32
-;tc 0 wred max = 64 64 64
-;tc 0 wred inv prob = 10 10 10
-;tc 0 wred weight = 9 9 9
-
-;tc 1 wred min = 48 40 32
-;tc 1 wred max = 64 64 64
-;tc 1 wred inv prob = 10 10 10
-;tc 1 wred weight = 9 9 9
-
-;tc 2 wred min = 48 40 32
-;tc 2 wred max = 64 64 64
-;tc 2 wred inv prob = 10 10 10
-;tc 2 wred weight = 9 9 9
-
-;tc 3 wred min = 48 40 32
-;tc 3 wred max = 64 64 64
-;tc 3 wred inv prob = 10 10 10
-;tc 3 wred weight = 9 9 9
-
-;tc 4 wred min = 48 40 32
-;tc 4 wred max = 64 64 64
-;tc 4 wred inv prob = 10 10 10
-;tc 4 wred weight = 9 9 9
-
-;tc 5 wred min = 48 40 32
-;tc 5 wred max = 64 64 64
-;tc 5 wred inv prob = 10 10 10
-;tc 5 wred weight = 9 9 9
-
-;tc 6 wred min = 48 40 32
-;tc 6 wred max = 64 64 64
-;tc 6 wred inv prob = 10 10 10
-;tc 6 wred weight = 9 9 9
-
-;tc 7 wred min = 48 40 32
-;tc 7 wred max = 64 64 64
-;tc 7 wred inv prob = 10 10 10
-;tc 7 wred weight = 9 9 9
-
-;tc 8 wred min = 48 40 32
-;tc 8 wred max = 64 64 64
-;tc 8 wred inv prob = 10 10 10
-;tc 8 wred weight = 9 9 9
-
-;tc 9 wred min = 48 40 32
-;tc 9 wred max = 64 64 64
-;tc 9 wred inv prob = 10 10 10
-;tc 9 wred weight = 9 9 9
-
-;tc 10 wred min = 48 40 32
-;tc 10 wred max = 64 64 64
-;tc 10 wred inv prob = 10 10 10
-;tc 10 wred weight = 9 9 9
-
-;tc 11 wred min = 48 40 32
-;tc 11 wred max = 64 64 64
-;tc 11 wred inv prob = 10 10 10
-;tc 11 wred weight = 9 9 9
-
-;tc 12 wred min = 48 40 32
-;tc 12 wred max = 64 64 64
-;tc 12 wred inv prob = 10 10 10
-;tc 12 wred weight = 9 9 9
-
-[pie]
-tc 0 qdelay ref = 15
-tc 0 max burst = 150
-tc 0 update interval = 15
-tc 0 tailq th = 64
-
-tc 1 qdelay ref = 15
-tc 1 max burst = 150
-tc 1 update interval = 15
-tc 1 tailq th = 64
-
-tc 2 qdelay ref = 15
-tc 2 max burst = 150
-tc 2 update interval = 15
-tc 2 tailq th = 64
-
-tc 3 qdelay ref = 15
-tc 3 max burst = 150
-tc 3 update interval = 15
-tc 3 tailq th = 64
-
-tc 4 qdelay ref = 15
-tc 4 max burst = 150
-tc 4 update interval = 15
-tc 4 tailq th = 64
-
-tc 5 qdelay ref = 15
-tc 5 max burst = 150
-tc 5 update interval = 15
-tc 5 tailq th = 64
-
-tc 6 qdelay ref = 15
-tc 6 max burst = 150
-tc 6 update interval = 15
-tc 6 tailq th = 64
-
-tc 7 qdelay ref = 15
-tc 7 max burst = 150
-tc 7 update interval = 15
-tc 7 tailq th = 64
-
-tc 8 qdelay ref = 15
-tc 8 max burst = 150
-tc 8 update interval = 15
-tc 8 tailq th = 64
-
-tc 9 qdelay ref = 15
-tc 9 max burst = 150
-tc 9 update interval = 15
-tc 9 tailq th = 64
-
-tc 10 qdelay ref = 15
-tc 10 max burst = 150
-tc 10 update interval = 15
-tc 10 tailq th = 64
-
-tc 11 qdelay ref = 15
-tc 11 max burst = 150
-tc 11 update interval = 15
-tc 11 tailq th = 64
-
-tc 12 qdelay ref = 15
-tc 12 max burst = 150
-tc 12 update interval = 15
-tc 12 tailq th = 64
+tc 12 wrr weights = 1 1 1 1
\ No newline at end of file
diff --git a/examples/qos_sched/profile_pie.cfg b/examples/qos_sched/profile_pie.cfg
new file mode 100644
index 0000000000..241f748b33
--- /dev/null
+++ b/examples/qos_sched/profile_pie.cfg
@@ -0,0 +1,142 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+[pie]
+tc 0 qdelay ref = 15
+tc 0 max burst = 150
+tc 0 update interval = 15
+tc 0 tailq th = 64
+
+tc 1 qdelay ref = 15
+tc 1 max burst = 150
+tc 1 update interval = 15
+tc 1 tailq th = 64
+
+tc 2 qdelay ref = 15
+tc 2 max burst = 150
+tc 2 update interval = 15
+tc 2 tailq th = 64
+
+tc 3 qdelay ref = 15
+tc 3 max burst = 150
+tc 3 update interval = 15
+tc 3 tailq th = 64
+
+tc 4 qdelay ref = 15
+tc 4 max burst = 150
+tc 4 update interval = 15
+tc 4 tailq th = 64
+
+tc 5 qdelay ref = 15
+tc 5 max burst = 150
+tc 5 update interval = 15
+tc 5 tailq th = 64
+
+tc 6 qdelay ref = 15
+tc 6 max burst = 150
+tc 6 update interval = 15
+tc 6 tailq th = 64
+
+tc 7 qdelay ref = 15
+tc 7 max burst = 150
+tc 7 update interval = 15
+tc 7 tailq th = 64
+
+tc 8 qdelay ref = 15
+tc 8 max burst = 150
+tc 8 update interval = 15
+tc 8 tailq th = 64
+
+tc 9 qdelay ref = 15
+tc 9 max burst = 150
+tc 9 update interval = 15
+tc 9 tailq th = 64
+
+tc 10 qdelay ref = 15
+tc 10 max burst = 150
+tc 10 update interval = 15
+tc 10 tailq th = 64
+
+tc 11 qdelay ref = 15
+tc 11 max burst = 150
+tc 11 update interval = 15
+tc 11 tailq th = 64
+
+tc 12 qdelay ref = 15
+tc 12 max burst = 150
+tc 12 update interval = 15
+tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_red.cfg b/examples/qos_sched/profile_red.cfg
new file mode 100644
index 0000000000..4486d2799e
--- /dev/null
+++ b/examples/qos_sched/profile_red.cfg
@@ -0,0 +1,143 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+; RED params per traffic class and color (Green / Yellow / Red)
+[red]
+tc 0 wred min = 48 40 32
+tc 0 wred max = 64 64 64
+tc 0 wred inv prob = 10 10 10
+tc 0 wred weight = 9 9 9
+
+tc 1 wred min = 48 40 32
+tc 1 wred max = 64 64 64
+tc 1 wred inv prob = 10 10 10
+tc 1 wred weight = 9 9 9
+
+tc 2 wred min = 48 40 32
+tc 2 wred max = 64 64 64
+tc 2 wred inv prob = 10 10 10
+tc 2 wred weight = 9 9 9
+
+tc 3 wred min = 48 40 32
+tc 3 wred max = 64 64 64
+tc 3 wred inv prob = 10 10 10
+tc 3 wred weight = 9 9 9
+
+tc 4 wred min = 48 40 32
+tc 4 wred max = 64 64 64
+tc 4 wred inv prob = 10 10 10
+tc 4 wred weight = 9 9 9
+
+tc 5 wred min = 48 40 32
+tc 5 wred max = 64 64 64
+tc 5 wred inv prob = 10 10 10
+tc 5 wred weight = 9 9 9
+
+tc 6 wred min = 48 40 32
+tc 6 wred max = 64 64 64
+tc 6 wred inv prob = 10 10 10
+tc 6 wred weight = 9 9 9
+
+tc 7 wred min = 48 40 32
+tc 7 wred max = 64 64 64
+tc 7 wred inv prob = 10 10 10
+tc 7 wred weight = 9 9 9
+
+tc 8 wred min = 48 40 32
+tc 8 wred max = 64 64 64
+tc 8 wred inv prob = 10 10 10
+tc 8 wred weight = 9 9 9
+
+tc 9 wred min = 48 40 32
+tc 9 wred max = 64 64 64
+tc 9 wred inv prob = 10 10 10
+tc 9 wred weight = 9 9 9
+
+tc 10 wred min = 48 40 32
+tc 10 wred max = 64 64 64
+tc 10 wred inv prob = 10 10 10
+tc 10 wred weight = 9 9 9
+
+tc 11 wred min = 48 40 32
+tc 11 wred max = 64 64 64
+tc 11 wred inv prob = 10 10 10
+tc 11 wred weight = 9 9 9
+
+tc 12 wred min = 48 40 32
+tc 12 wred max = 64 64 64
+tc 12 wred inv prob = 10 10 10
+tc 12 wred weight = 9 9 9
diff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c
index 599c7e9536..c5fa9e4582 100644
--- a/lib/sched/rte_sched.c
+++ b/lib/sched/rte_sched.c
@@ -81,13 +81,11 @@ struct rte_sched_queue {
struct rte_sched_queue_extra {
struct rte_sched_queue_stats stats;
-#ifdef RTE_SCHED_CMAN
RTE_STD_C11
union {
struct rte_red red;
struct rte_pie pie;
};
-#endif
};
enum grinder_state {
@@ -179,7 +177,6 @@ struct rte_sched_subport {
/* Pipe queues size */
uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
-#ifdef RTE_SCHED_CMAN
bool cman_enabled;
enum rte_sched_cman_mode cman;
@@ -188,7 +185,6 @@ struct rte_sched_subport {
struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];
struct rte_pie_config pie_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
};
-#endif
/* Scheduling loop detection */
uint32_t pipe_loop;
@@ -1084,7 +1080,6 @@ rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports)
rte_free(port);
}
-#ifdef RTE_SCHED_CMAN
static int
rte_sched_red_config(struct rte_sched_port *port,
struct rte_sched_subport *s,
@@ -1166,7 +1161,6 @@ rte_sched_cman_config(struct rte_sched_port *port,
return -EINVAL;
}
-#endif
int
rte_sched_subport_tc_ov_config(struct rte_sched_port *port,
@@ -1285,7 +1279,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
/* TC oversubscription is enabled by default */
s->tc_ov_enabled = 1;
-#ifdef RTE_SCHED_CMAN
if (params->cman_params != NULL) {
s->cman_enabled = true;
status = rte_sched_cman_config(port, s, params, n_subports);
@@ -1297,7 +1290,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
} else {
s->cman_enabled = false;
}
-#endif
/* Scheduling loop detection */
s->pipe_loop = RTE_SCHED_PIPE_INVALID;
@@ -1823,7 +1815,7 @@ rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
uint32_t tc_index = rte_sched_port_pipe_tc(port, qindex);
uint32_t pkt_len = pkt->pkt_len;
@@ -1849,21 +1841,17 @@ static inline void
rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
uint32_t pkt_len = pkt->pkt_len;
qe->stats.n_pkts_dropped += 1;
qe->stats.n_bytes_dropped += pkt_len;
-#ifdef RTE_SCHED_CMAN
if (subport->cman_enabled)
qe->stats.n_pkts_cman_dropped += n_pkts_cman_dropped;
-#endif
}
-#ifdef RTE_SCHED_CMAN
-
static inline int
rte_sched_port_cman_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
@@ -1908,13 +1896,11 @@ static inline void
rte_sched_port_red_set_queue_empty_timestamp(struct rte_sched_port *port,
struct rte_sched_subport *subport, uint32_t qindex)
{
- if (subport->cman_enabled) {
+ if (subport->cman_enabled && subport->cman == RTE_SCHED_CMAN_RED) {
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
- if (subport->cman == RTE_SCHED_CMAN_RED) {
- struct rte_red *red = &qe->red;
+ struct rte_red *red = &qe->red;
- rte_red_mark_queue_empty(red, port->time);
- }
+ rte_red_mark_queue_empty(red, port->time);
}
}
@@ -1933,29 +1919,6 @@ uint32_t qindex, uint32_t pkt_len, uint64_t time) {
}
}
-#else
-
-static inline int rte_sched_port_cman_drop(struct rte_sched_port *port __rte_unused,
- struct rte_sched_subport *subport __rte_unused,
- struct rte_mbuf *pkt __rte_unused,
- uint32_t qindex __rte_unused,
- uint16_t qlen __rte_unused)
-{
- return 0;
-}
-
-#define rte_sched_port_red_set_queue_empty_timestamp(port, subport, qindex)
-
-static inline void
-rte_sched_port_pie_dequeue(struct rte_sched_subport *subport __rte_unused,
- uint32_t qindex __rte_unused,
- uint32_t pkt_len __rte_unused,
- uint64_t time __rte_unused) {
- /* do-nothing when RTE_SCHED_CMAN not defined */
-}
-
-#endif /* RTE_SCHED_CMAN */
-
#ifdef RTE_SCHED_DEBUG
static inline void
--
2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v8] sched: enable CMAN at runtime
2022-07-05 17:05 ` [PATCH v8] " Marcin Danilewicz
@ 2022-07-05 18:00 ` Ajmera, Megha
2022-07-05 22:26 ` Danilewicz, MarcinX
2022-07-06 8:53 ` Singh, Jasvinder
2022-07-08 13:14 ` [PATCH v9] " Marcin Danilewicz
2 siblings, 1 reply; 27+ messages in thread
From: Ajmera, Megha @ 2022-07-05 18:00 UTC (permalink / raw)
To: Danilewicz, MarcinX, dev, Singh, Jasvinder, Dumitrescu, Cristian
>
> Added changes to enable CMAN (RED or PIE) at init from profile configuration
> file.
>
> By default CMAN code is enable but not in use, when there is no RED or PIE
> profile configured.
>
> Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
> ---
> Log: v2 change in rte_sched.h to avoid ABI breakage.
> v3 changes from comments
> v4 rebase to 22.07-rc1
> v5 rebase to main latest
> v6 commit message fixed
> v7 changes from comments
> v8 with changes from comments
> ---
> config/rte_config.h | 3 -
> drivers/net/softnic/rte_eth_softnic_tm.c | 12 --
> examples/ip_pipeline/tmgr.c | 4 -
> examples/qos_sched/cfg_file.c | 47 +-------
> examples/qos_sched/cfg_file.h | 5 -
> examples/qos_sched/init.c | 76 +-----------
> examples/qos_sched/main.h | 2 -
> examples/qos_sched/profile.cfg | 135 +--------------------
> examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++
> examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++
> lib/sched/rte_sched.c | 47 +-------
> 11 files changed, 296 insertions(+), 320 deletions(-) create mode 100644
> examples/qos_sched/profile_pie.cfg
> create mode 100644 examples/qos_sched/profile_red.cfg
>
> diff --git a/config/rte_config.h b/config/rte_config.h index
> 46549cb062..ae56a86394 100644
> --- a/config/rte_config.h
> +++ b/config/rte_config.h
> @@ -88,9 +88,6 @@
> /* rte_power defines */
> #define RTE_MAX_LCORE_FREQS 64
>
> -/* rte_sched defines */
> -// RTE_SCHED_CMAN is not set
> -
> /* rte_graph defines */
> #define RTE_GRAPH_BURST_SIZE 256
> #define RTE_LIBRTE_GRAPH_STATS 1
> diff --git a/drivers/net/softnic/rte_eth_softnic_tm.c
> b/drivers/net/softnic/rte_eth_softnic_tm.c
> index 6a7766ba1c..3e4bed81e9 100644
> --- a/drivers/net/softnic/rte_eth_softnic_tm.c
> +++ b/drivers/net/softnic/rte_eth_softnic_tm.c
> @@ -420,11 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,
> return 0;
> }
>
> -#ifdef RTE_SCHED_CMAN
> -#define WRED_SUPPORTED 1
> -#else
> #define WRED_SUPPORTED 0
> -#endif
>
> #define STATS_MASK_DEFAULT \
> (RTE_TM_STATS_N_PKTS | \
> @@ -2300,8 +2296,6 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev,
> uint32_t tc_id)
> return NULL;
> }
>
> -#ifdef RTE_SCHED_CMAN
> -
> static void
> wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id) { @@ -
> 2325,12 +2319,6 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t
> subport_id)
> }
> }
>
> -#else
> -
> -#define wred_profiles_set(dev, subport_id)
> -
> -#endif
> -
> static struct tm_shared_shaper *
> tm_tc_shared_shaper_get(struct rte_eth_dev *dev, struct tm_node *tc_node) {
> diff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c index
> b138e885cf..e68e9961be 100644
> --- a/examples/ip_pipeline/tmgr.c
> +++ b/examples/ip_pipeline/tmgr.c
> @@ -17,7 +17,6 @@ static uint32_t n_subport_profiles; static struct
> rte_sched_pipe_params
> pipe_profile[TMGR_PIPE_PROFILE_MAX];
>
> -#ifdef RTE_SCHED_CMAN
> static struct rte_sched_cman_params cman_params = {
> .red_params = {
> /* Traffic Class 0 Colors Green / Yellow / Red */ @@ -86,7
> +85,6 @@ static struct rte_sched_cman_params cman_params = {
> [12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2
> = 9},
> },
> };
> -#endif /* RTE_SCHED_CMAN */
>
> static uint32_t n_pipe_profiles;
>
> @@ -96,9 +94,7 @@ static const struct rte_sched_subport_params
> subport_params_default = {
> .pipe_profiles = pipe_profile,
> .n_pipe_profiles = 0, /* filled at run time */
> .n_max_pipe_profiles = RTE_DIM(pipe_profile), -#ifdef
> RTE_SCHED_CMAN
> .cman_params = &cman_params,
> -#endif /* RTE_SCHED_CMAN */
> };
>
> static struct tmgr_port_list tmgr_port_list; diff --git
> a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c index
> 450482f07d..7f4114bd56 100644
> --- a/examples/qos_sched/cfg_file.c
> +++ b/examples/qos_sched/cfg_file.c
> @@ -23,6 +23,8 @@
> uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
> uint32_t n_active_queues;
>
> +struct rte_sched_cman_params cman_params;
> +
> int
> cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params
> *port_params) { @@ -229,40 +231,6 @@ cfg_load_subport_profile(struct
> rte_cfgfile *cfg,
> return 0;
> }
>
> -#ifdef RTE_SCHED_CMAN
> -void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
> - struct rte_sched_cman_params
> cman_p)
> -{
> - int j, k;
> - subport_p->cman_params->cman_mode = cman_p.cman_mode;
> -
> - for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
> - if (subport_p->cman_params->cman_mode ==
> - RTE_SCHED_CMAN_RED) {
> - for (k = 0; k < RTE_COLORS; k++) {
> - subport_p->cman_params-
> >red_params[j][k].min_th =
> - cman_p.red_params[j][k].min_th;
> - subport_p->cman_params-
> >red_params[j][k].max_th =
> - cman_p.red_params[j][k].max_th;
> - subport_p->cman_params-
> >red_params[j][k].maxp_inv =
> - cman_p.red_params[j][k].maxp_inv;
> - subport_p->cman_params-
> >red_params[j][k].wq_log2 =
> - cman_p.red_params[j][k].wq_log2;
> - }
> - } else {
> - subport_p->cman_params->pie_params[j].qdelay_ref =
> - cman_p.pie_params[j].qdelay_ref;
> - subport_p->cman_params-
> >pie_params[j].dp_update_interval =
> - cman_p.pie_params[j].dp_update_interval;
> - subport_p->cman_params->pie_params[j].max_burst =
> - cman_p.pie_params[j].max_burst;
> - subport_p->cman_params->pie_params[j].tailq_th =
> - cman_p.pie_params[j].tailq_th;
> - }
> - }
> -}
> -#endif
> -
> int
> cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params
> *subport_params) { @@ -276,11 +244,7 @@ cfg_load_subport(struct
> rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
> memset(active_queues, 0, sizeof(active_queues));
> n_active_queues = 0;
>
> -#ifdef RTE_SCHED_CMAN
> - struct rte_sched_cman_params cman_params = {
> - .cman_mode = RTE_SCHED_CMAN_RED,
> - .red_params = { },
> - };
> + subport_params->cman_params = NULL;
>
> if (rte_cfgfile_has_section(cfg, "red")) {
> cman_params.cman_mode = RTE_SCHED_CMAN_RED; @@ -
> 387,7 +351,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct
> rte_sched_subport_params *subpo
>
> }
> }
Here only mode is set to RTE_SCHED_CMAN_RED. But I could not find the place where cman_params are set from cfg_file (for e.g. red_params). Can you clarify?
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v8] sched: enable CMAN at runtime
2022-07-05 18:00 ` Ajmera, Megha
@ 2022-07-05 22:26 ` Danilewicz, MarcinX
0 siblings, 0 replies; 27+ messages in thread
From: Danilewicz, MarcinX @ 2022-07-05 22:26 UTC (permalink / raw)
To: Ajmera, Megha, dev, Singh, Jasvinder, Dumitrescu, Cristian
<snip>
> Here only mode is set to RTE_SCHED_CMAN_RED. But I could not find the
> place where cman_params are set from cfg_file (for e.g. red_params). Can
> you clarify?
Look beyond that particular change. All this is joined work. I am adding final touch to what I've started, he continued and now we all are close to push changes.
Take a look here at that particular file history:
06135957c4b (Wojciech Liguzinski 2021-11-04 11:03:34 +0000 353)
06135957c4b (Wojciech Liguzinski 2021-11-04 11:03:34 +0000 354) if (rte_cfgfile_has_section(cfg, "pie")) {
06135957c4b (Wojciech Liguzinski 2021-11-04 11:03:34 +0000 355) cman_params.cman_mode = RTE_SCHED_CMAN_PIE;
06135957c4b (Wojciech Liguzinski 2021-11-04 11:03:34 +0000 356)
06135957c4b (Wojciech Liguzinski 2021-11-04 11:03:34 +0000 357) for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
06135957c4b (Wojciech Liguzinski 2021-11-04 11:03:34 +0000 358) char str[32];
Hope that helps 😊
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v8] sched: enable CMAN at runtime
2022-07-05 17:05 ` [PATCH v8] " Marcin Danilewicz
2022-07-05 18:00 ` Ajmera, Megha
@ 2022-07-06 8:53 ` Singh, Jasvinder
2022-07-07 13:07 ` Danilewicz, MarcinX
2022-07-08 13:14 ` [PATCH v9] " Marcin Danilewicz
2 siblings, 1 reply; 27+ messages in thread
From: Singh, Jasvinder @ 2022-07-06 8:53 UTC (permalink / raw)
To: Danilewicz, MarcinX, dev, Dumitrescu, Cristian; +Cc: Ajmera, Megha
> -----Original Message-----
> From: Danilewicz, MarcinX <marcinx.danilewicz@intel.com>
> Sent: Tuesday, July 5, 2022 6:06 PM
> To: dev@dpdk.org; Singh, Jasvinder <jasvinder.singh@intel.com>;
> Dumitrescu, Cristian <cristian.dumitrescu@intel.com>
> Cc: Ajmera, Megha <megha.ajmera@intel.com>
> Subject: [PATCH v8] sched: enable CMAN at runtime
>
> Added changes to enable CMAN (RED or PIE) at init from profile configuration
> file.
>
> By default CMAN code is enable but not in use, when there is no RED or PIE
> profile configured.
>
> Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
> ---
> Log: v2 change in rte_sched.h to avoid ABI breakage.
> v3 changes from comments
> v4 rebase to 22.07-rc1
> v5 rebase to main latest
> v6 commit message fixed
> v7 changes from comments
> v8 with changes from comments
You need to explicitly mention the changes done in each version to help reviewer easily locate the changes.
> config/rte_config.h | 3 -
> drivers/net/softnic/rte_eth_softnic_tm.c | 12 --
> examples/ip_pipeline/tmgr.c | 4 -
> examples/qos_sched/cfg_file.c | 47 +-------
> examples/qos_sched/cfg_file.h | 5 -
> examples/qos_sched/init.c | 76 +-----------
> examples/qos_sched/main.h | 2 -
> examples/qos_sched/profile.cfg | 135 +--------------------
> examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++
> examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++
> lib/sched/rte_sched.c | 47 +-------
> 11 files changed, 296 insertions(+), 320 deletions(-) create mode 100644
> examples/qos_sched/profile_pie.cfg
> create mode 100644 examples/qos_sched/profile_red.cfg
>
> diff --git a/config/rte_config.h b/config/rte_config.h index
> 46549cb062..ae56a86394 100644
> --- a/config/rte_config.h
> +++ b/config/rte_config.h
> @@ -88,9 +88,6 @@
> /* rte_power defines */
> #define RTE_MAX_LCORE_FREQS 64
>
> -/* rte_sched defines */
> -// RTE_SCHED_CMAN is not set
> -
> /* rte_graph defines */
> #define RTE_GRAPH_BURST_SIZE 256
> #define RTE_LIBRTE_GRAPH_STATS 1
> diff --git a/drivers/net/softnic/rte_eth_softnic_tm.c
> b/drivers/net/softnic/rte_eth_softnic_tm.c
> index 6a7766ba1c..3e4bed81e9 100644
> --- a/drivers/net/softnic/rte_eth_softnic_tm.c
> +++ b/drivers/net/softnic/rte_eth_softnic_tm.c
> @@ -420,11 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,
> return 0;
> }
>
> -#ifdef RTE_SCHED_CMAN
> -#define WRED_SUPPORTED 1
> -#else
> #define WRED_SUPPORTED 0
> -#endif
>
> #define STATS_MASK_DEFAULT \
> (RTE_TM_STATS_N_PKTS | \
> @@ -2300,8 +2296,6 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev,
> uint32_t tc_id)
> return NULL;
> }
>
> -#ifdef RTE_SCHED_CMAN
> -
> static void
> wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id) { @@ -
> 2325,12 +2319,6 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t
> subport_id)
> }
> }
>
> -#else
> -
> -#define wred_profiles_set(dev, subport_id)
> -
> -#endif
> -
> static struct tm_shared_shaper *
> tm_tc_shared_shaper_get(struct rte_eth_dev *dev, struct tm_node
> *tc_node) { diff --git a/examples/ip_pipeline/tmgr.c
> b/examples/ip_pipeline/tmgr.c index b138e885cf..e68e9961be 100644
> --- a/examples/ip_pipeline/tmgr.c
> +++ b/examples/ip_pipeline/tmgr.c
> @@ -17,7 +17,6 @@ static uint32_t n_subport_profiles; static struct
> rte_sched_pipe_params
> pipe_profile[TMGR_PIPE_PROFILE_MAX];
>
> -#ifdef RTE_SCHED_CMAN
> static struct rte_sched_cman_params cman_params = {
> .red_params = {
> /* Traffic Class 0 Colors Green / Yellow / Red */ @@ -86,7
> +85,6 @@ static struct rte_sched_cman_params cman_params = {
> [12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10,
> .wq_log2 = 9},
> },
> };
> -#endif /* RTE_SCHED_CMAN */
>
> static uint32_t n_pipe_profiles;
>
> @@ -96,9 +94,7 @@ static const struct rte_sched_subport_params
> subport_params_default = {
> .pipe_profiles = pipe_profile,
> .n_pipe_profiles = 0, /* filled at run time */
> .n_max_pipe_profiles = RTE_DIM(pipe_profile), -#ifdef
> RTE_SCHED_CMAN
> .cman_params = &cman_params,
> -#endif /* RTE_SCHED_CMAN */
> };
Similar to what is discussed for qos_sched sample app, set cman_params to NULL and remove default parameters for "static struct rte_sched_cman_params cman_params" above.
> static struct tmgr_port_list tmgr_port_list; diff --git
> a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c index
> 450482f07d..7f4114bd56 100644
> --- a/examples/qos_sched/cfg_file.c
> +++ b/examples/qos_sched/cfg_file.c
> @@ -23,6 +23,8 @@
> uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
> uint32_t n_active_queues;
>
> +struct rte_sched_cman_params cman_params;
> +
> int
> cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params
> *port_params) { @@ -229,40 +231,6 @@ cfg_load_subport_profile(struct
> rte_cfgfile *cfg,
> return 0;
> }
>
> -#ifdef RTE_SCHED_CMAN
> -void set_subport_cman_params(struct rte_sched_subport_params
> *subport_p,
> - struct rte_sched_cman_params
> cman_p)
> -{
> - int j, k;
> - subport_p->cman_params->cman_mode = cman_p.cman_mode;
> -
> - for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
> - if (subport_p->cman_params->cman_mode ==
> - RTE_SCHED_CMAN_RED) {
> - for (k = 0; k < RTE_COLORS; k++) {
> - subport_p->cman_params-
> >red_params[j][k].min_th =
> - cman_p.red_params[j][k].min_th;
> - subport_p->cman_params-
> >red_params[j][k].max_th =
> - cman_p.red_params[j][k].max_th;
> - subport_p->cman_params-
> >red_params[j][k].maxp_inv =
> - cman_p.red_params[j][k].maxp_inv;
> - subport_p->cman_params-
> >red_params[j][k].wq_log2 =
> - cman_p.red_params[j][k].wq_log2;
> - }
> - } else {
> - subport_p->cman_params-
> >pie_params[j].qdelay_ref =
> - cman_p.pie_params[j].qdelay_ref;
> - subport_p->cman_params-
> >pie_params[j].dp_update_interval =
> - cman_p.pie_params[j].dp_update_interval;
> - subport_p->cman_params-
> >pie_params[j].max_burst =
> - cman_p.pie_params[j].max_burst;
> - subport_p->cman_params->pie_params[j].tailq_th =
> - cman_p.pie_params[j].tailq_th;
> - }
> - }
> -}
> -#endif
> -
> int
> cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params
> *subport_params) { @@ -276,11 +244,7 @@ cfg_load_subport(struct
> rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
> memset(active_queues, 0, sizeof(active_queues));
> n_active_queues = 0;
>
> -#ifdef RTE_SCHED_CMAN
> - struct rte_sched_cman_params cman_params = {
> - .cman_mode = RTE_SCHED_CMAN_RED,
> - .red_params = { },
> - };
> + subport_params->cman_params = NULL;
No need to set subport_params->cman_params again to null as it is already set to NULL in init.c.
> if (rte_cfgfile_has_section(cfg, "red")) {
> cman_params.cman_mode = RTE_SCHED_CMAN_RED; @@ -
> 387,7 +351,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct
> rte_sched_subport_params *subpo
>
> }
> }
> -#endif /* RTE_SCHED_CMAN */
>
> for (i = 0; i < MAX_SCHED_SUBPORTS; i++) {
> char sec_name[CFG_NAME_LEN];
> @@ -465,9 +428,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct
> rte_sched_subport_params *subpo
> }
> }
> }
> -#ifdef RTE_SCHED_CMAN
> - set_subport_cman_params(subport_params+i,
> cman_params);
> -#endif
> + subport_params[i].cman_params = &cman_params;
Since cman_params_is global variable, memory is allocated regardless of whether cman mechanism is enabled or disabled. So subport_params->cman_params will never point to NULL even when red/pie is disabled. Define local flag "cman_enabled" and set his flag if red or pie is enabled and check this flag to set subport_params[i].cman_params to cman_params.
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v8] sched: enable CMAN at runtime
2022-07-06 8:53 ` Singh, Jasvinder
@ 2022-07-07 13:07 ` Danilewicz, MarcinX
2022-07-07 16:28 ` Singh, Jasvinder
0 siblings, 1 reply; 27+ messages in thread
From: Danilewicz, MarcinX @ 2022-07-07 13:07 UTC (permalink / raw)
To: Singh, Jasvinder, dev, Dumitrescu, Cristian; +Cc: Ajmera, Megha
<snip>
> > Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
> > ---
> > Log: v2 change in rte_sched.h to avoid ABI breakage.
> > v3 changes from comments
> > v4 rebase to 22.07-rc1
> > v5 rebase to main latest
> > v6 commit message fixed
> > v7 changes from comments
> > v8 with changes from comments
>
>
> You need to explicitly mention the changes done in each version to help
> reviewer easily locate the changes.
Yes, yes. I am going to provide more detailed changes and explaining history on what changes was made. This split development over time is the best example to show that need.
<snip>
>>@@ -96,9 +94,7 @@ static const struct rte_sched_subport_params
> > subport_params_default = {
> > .pipe_profiles = pipe_profile,
> > .n_pipe_profiles = 0, /* filled at run time */
> > .n_max_pipe_profiles = RTE_DIM(pipe_profile), -#ifdef
> RTE_SCHED_CMAN
> > .cman_params = &cman_params,
> > -#endif /* RTE_SCHED_CMAN */
> > };
>
>
> Similar to what is discussed for qos_sched sample app, set cman_params to
> NULL and remove default parameters for "static struct
> rte_sched_cman_params cman_params" above.
Sure, that will be done.
> > -#ifdef RTE_SCHED_CMAN
> > - struct rte_sched_cman_params cman_params = {
> > - .cman_mode = RTE_SCHED_CMAN_RED,
> > - .red_params = { },
> > - };
> > + subport_params->cman_params = NULL;
>
> No need to set subport_params->cman_params again to null as it is already
> set to NULL in init.c.
Sure, app_load_cfg_profile -> cfg_load_subport is also not called several times, just once
<snip>
> > }
> > -#ifdef RTE_SCHED_CMAN
> > - set_subport_cman_params(subport_params+i,
> > cman_params);
> > -#endif
> > + subport_params[i].cman_params = &cman_params;
>
> Since cman_params_is global variable, memory is allocated regardless of
> whether cman mechanism is enabled or disabled. So subport_params-
> >cman_params will never point to NULL even when red/pie is disabled.
> Define local flag "cman_enabled" and set his flag if red or pie is enabled and
> check this flag to set subport_params[i].cman_params to cman_params.
Ah .. nice spot. But, cant we do that with additional check, using what we have?
For an instance:
If (cman_params.cman_mode == RTE_SCHED_CMAN_PIE || cman_params.cman_mode == RTE_SCHED_CMAN_RED) {
Then set subport_params[i].cman_params to cman_params.
}
BR,
/Marcin
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v8] sched: enable CMAN at runtime
2022-07-07 13:07 ` Danilewicz, MarcinX
@ 2022-07-07 16:28 ` Singh, Jasvinder
2022-07-07 21:22 ` Danilewicz, MarcinX
0 siblings, 1 reply; 27+ messages in thread
From: Singh, Jasvinder @ 2022-07-07 16:28 UTC (permalink / raw)
To: Danilewicz, MarcinX, dev, Dumitrescu, Cristian; +Cc: Ajmera, Megha
<snip>
> > > -#ifdef RTE_SCHED_CMAN
> > > - set_subport_cman_params(subport_params+i,
> > > cman_params);
> > > -#endif
> > > + subport_params[i].cman_params = &cman_params;
> >
> > Since cman_params_is global variable, memory is allocated regardless
> > of whether cman mechanism is enabled or disabled. So subport_params-
> > >cman_params will never point to NULL even when red/pie is disabled.
> > Define local flag "cman_enabled" and set his flag if red or pie is
> > enabled and check this flag to set subport_params[i].cman_params to
> cman_params.
> Ah .. nice spot. But, cant we do that with additional check, using what we
> have?
> For an instance:
> If (cman_params.cman_mode == RTE_SCHED_CMAN_PIE ||
> cman_params.cman_mode == RTE_SCHED_CMAN_RED) { Then set
> subport_params[i].cman_params to cman_params.
> }
Yes, this is correct as well.
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v8] sched: enable CMAN at runtime
2022-07-07 16:28 ` Singh, Jasvinder
@ 2022-07-07 21:22 ` Danilewicz, MarcinX
0 siblings, 0 replies; 27+ messages in thread
From: Danilewicz, MarcinX @ 2022-07-07 21:22 UTC (permalink / raw)
To: Singh, Jasvinder, dev, Dumitrescu, Cristian; +Cc: Ajmera, Megha
<snip>
> > For an instance:
> > If (cman_params.cman_mode == RTE_SCHED_CMAN_PIE ||
> > cman_params.cman_mode == RTE_SCHED_CMAN_RED) { Then set
> > subport_params[i].cman_params to cman_params.
> > }
>
> Yes, this is correct as well.
I'm happy to hear that.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v9] sched: enable CMAN at runtime
2022-07-05 17:05 ` [PATCH v8] " Marcin Danilewicz
2022-07-05 18:00 ` Ajmera, Megha
2022-07-06 8:53 ` Singh, Jasvinder
@ 2022-07-08 13:14 ` Marcin Danilewicz
2 siblings, 0 replies; 27+ messages in thread
From: Marcin Danilewicz @ 2022-07-08 13:14 UTC (permalink / raw)
To: dev, jasvinder.singh, cristian.dumitrescu; +Cc: megha.ajmera
Added changes to enable CMAN (RED or PIE) at init
from profile configuration file.
By default CMAN code is enable but not in use, when
there is no RED or PIE profile configured.
Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
---
Log: v2 change in rte_sched.h to avoid ABI breakage.
v3 changes from comments
v4 rebase to 22.07-rc1
v5 rebase to main latest
v6 commit message fixed
v7 changes from comments
v8 with changes from comments
v9 changes from comments
tmgr.c
cman_params set to null
qos_sched/cfg_file.c
removed redundant cman_params to NULL assignement
subport_params[].cman_params assigned
only when CMAN enabled
---
config/rte_config.h | 3 -
drivers/net/softnic/rte_eth_softnic_tm.c | 12 --
examples/ip_pipeline/tmgr.c | 6 +-
examples/qos_sched/cfg_file.c | 49 +-------
examples/qos_sched/cfg_file.h | 5 -
examples/qos_sched/init.c | 76 +-----------
examples/qos_sched/main.h | 2 -
examples/qos_sched/profile.cfg | 135 +--------------------
examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++
examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++
lib/sched/rte_sched.c | 47 +-------
11 files changed, 298 insertions(+), 322 deletions(-)
create mode 100644 examples/qos_sched/profile_pie.cfg
create mode 100644 examples/qos_sched/profile_red.cfg
diff --git a/config/rte_config.h b/config/rte_config.h
index 46549cb062..ae56a86394 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -88,9 +88,6 @@
/* rte_power defines */
#define RTE_MAX_LCORE_FREQS 64
-/* rte_sched defines */
-// RTE_SCHED_CMAN is not set
-
/* rte_graph defines */
#define RTE_GRAPH_BURST_SIZE 256
#define RTE_LIBRTE_GRAPH_STATS 1
diff --git a/drivers/net/softnic/rte_eth_softnic_tm.c b/drivers/net/softnic/rte_eth_softnic_tm.c
index 6a7766ba1c..3e4bed81e9 100644
--- a/drivers/net/softnic/rte_eth_softnic_tm.c
+++ b/drivers/net/softnic/rte_eth_softnic_tm.c
@@ -420,11 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,
return 0;
}
-#ifdef RTE_SCHED_CMAN
-#define WRED_SUPPORTED 1
-#else
#define WRED_SUPPORTED 0
-#endif
#define STATS_MASK_DEFAULT \
(RTE_TM_STATS_N_PKTS | \
@@ -2300,8 +2296,6 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev, uint32_t tc_id)
return NULL;
}
-#ifdef RTE_SCHED_CMAN
-
static void
wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
{
@@ -2325,12 +2319,6 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
}
}
-#else
-
-#define wred_profiles_set(dev, subport_id)
-
-#endif
-
static struct tm_shared_shaper *
tm_tc_shared_shaper_get(struct rte_eth_dev *dev, struct tm_node *tc_node)
{
diff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c
index b138e885cf..18bee1e0fc 100644
--- a/examples/ip_pipeline/tmgr.c
+++ b/examples/ip_pipeline/tmgr.c
@@ -17,7 +17,6 @@ static uint32_t n_subport_profiles;
static struct rte_sched_pipe_params
pipe_profile[TMGR_PIPE_PROFILE_MAX];
-#ifdef RTE_SCHED_CMAN
static struct rte_sched_cman_params cman_params = {
.red_params = {
/* Traffic Class 0 Colors Green / Yellow / Red */
@@ -86,7 +85,6 @@ static struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
static uint32_t n_pipe_profiles;
@@ -96,9 +94,7 @@ static const struct rte_sched_subport_params subport_params_default = {
.pipe_profiles = pipe_profile,
.n_pipe_profiles = 0, /* filled at run time */
.n_max_pipe_profiles = RTE_DIM(pipe_profile),
-#ifdef RTE_SCHED_CMAN
- .cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
+ .cman_params = NULL,
};
static struct tmgr_port_list tmgr_port_list;
diff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c
index 450482f07d..deaa28d391 100644
--- a/examples/qos_sched/cfg_file.c
+++ b/examples/qos_sched/cfg_file.c
@@ -23,6 +23,8 @@
uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
uint32_t n_active_queues;
+struct rte_sched_cman_params cman_params;
+
int
cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port_params)
{
@@ -229,40 +231,6 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg,
return 0;
}
-#ifdef RTE_SCHED_CMAN
-void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
- struct rte_sched_cman_params cman_p)
-{
- int j, k;
- subport_p->cman_params->cman_mode = cman_p.cman_mode;
-
- for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
- if (subport_p->cman_params->cman_mode ==
- RTE_SCHED_CMAN_RED) {
- for (k = 0; k < RTE_COLORS; k++) {
- subport_p->cman_params->red_params[j][k].min_th =
- cman_p.red_params[j][k].min_th;
- subport_p->cman_params->red_params[j][k].max_th =
- cman_p.red_params[j][k].max_th;
- subport_p->cman_params->red_params[j][k].maxp_inv =
- cman_p.red_params[j][k].maxp_inv;
- subport_p->cman_params->red_params[j][k].wq_log2 =
- cman_p.red_params[j][k].wq_log2;
- }
- } else {
- subport_p->cman_params->pie_params[j].qdelay_ref =
- cman_p.pie_params[j].qdelay_ref;
- subport_p->cman_params->pie_params[j].dp_update_interval =
- cman_p.pie_params[j].dp_update_interval;
- subport_p->cman_params->pie_params[j].max_burst =
- cman_p.pie_params[j].max_burst;
- subport_p->cman_params->pie_params[j].tailq_th =
- cman_p.pie_params[j].tailq_th;
- }
- }
-}
-#endif
-
int
cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)
{
@@ -276,12 +244,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
memset(active_queues, 0, sizeof(active_queues));
n_active_queues = 0;
-#ifdef RTE_SCHED_CMAN
- struct rte_sched_cman_params cman_params = {
- .cman_mode = RTE_SCHED_CMAN_RED,
- .red_params = { },
- };
-
if (rte_cfgfile_has_section(cfg, "red")) {
cman_params.cman_mode = RTE_SCHED_CMAN_RED;
@@ -387,7 +349,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
-#endif /* RTE_SCHED_CMAN */
for (i = 0; i < MAX_SCHED_SUBPORTS; i++) {
char sec_name[CFG_NAME_LEN];
@@ -465,9 +426,9 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
}
-#ifdef RTE_SCHED_CMAN
- set_subport_cman_params(subport_params+i, cman_params);
-#endif
+ if (cman_params.cman_mode == RTE_SCHED_CMAN_PIE ||
+ cman_params.cman_mode == RTE_SCHED_CMAN_RED)
+ subport_params[i].cman_params = &cman_params;
}
}
diff --git a/examples/qos_sched/cfg_file.h b/examples/qos_sched/cfg_file.h
index 1a9dce9db5..0dc458aa71 100644
--- a/examples/qos_sched/cfg_file.h
+++ b/examples/qos_sched/cfg_file.h
@@ -12,11 +12,6 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);
int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);
-#ifdef RTE_SCHED_CMAN
-void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
- struct rte_sched_cman_params cman_p);
-#endif
-
int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);
int cfg_load_subport_profile(struct rte_cfgfile *cfg,
diff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c
index 8a0fb8a374..e8b819ffb9 100644
--- a/examples/qos_sched/init.c
+++ b/examples/qos_sched/init.c
@@ -201,78 +201,6 @@ static struct rte_sched_subport_profile_params
},
};
-#ifdef RTE_SCHED_CMAN
-struct rte_sched_cman_params cman_params = {
- .cman_mode = RTE_SCHED_CMAN_RED,
- .red_params = {
- /* Traffic Class 0 Colors Green / Yellow / Red */
- [0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 1 - Colors Green / Yellow / Red */
- [1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 2 - Colors Green / Yellow / Red */
- [2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 3 - Colors Green / Yellow / Red */
- [3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 4 - Colors Green / Yellow / Red */
- [4][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [4][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [4][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 5 - Colors Green / Yellow / Red */
- [5][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [5][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [5][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 6 - Colors Green / Yellow / Red */
- [6][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [6][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [6][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 7 - Colors Green / Yellow / Red */
- [7][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [7][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [7][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 8 - Colors Green / Yellow / Red */
- [8][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [8][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [8][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 9 - Colors Green / Yellow / Red */
- [9][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [9][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [9][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 10 - Colors Green / Yellow / Red */
- [10][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [10][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [10][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 11 - Colors Green / Yellow / Red */
- [11][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [11][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [11][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 12 - Colors Green / Yellow / Red */
- [12][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- },
-};
-#endif /* RTE_SCHED_CMAN */
-
struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
{
.n_pipes_per_subport_enabled = 4096,
@@ -281,9 +209,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
.n_pipe_profiles = sizeof(pipe_profiles) /
sizeof(struct rte_sched_pipe_params),
.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,
-#ifdef RTE_SCHED_CMAN
- .cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
+ .cman_params = NULL,
},
};
diff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h
index 915311bac8..76a68f585f 100644
--- a/examples/qos_sched/main.h
+++ b/examples/qos_sched/main.h
@@ -153,9 +153,7 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
extern uint32_t n_active_queues;
extern struct rte_sched_port_params port_params;
-#ifdef RTE_SCHED_CMAN
extern struct rte_sched_cman_params cman_params;
-#endif
extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];
int app_parse_args(int argc, char **argv);
diff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg
index d4b21c0170..c9ec187c93 100644
--- a/examples/qos_sched/profile.cfg
+++ b/examples/qos_sched/profile.cfg
@@ -73,137 +73,4 @@ tc period = 40 ; Milliseconds
tc 12 oversubscription weight = 1
-tc 12 wrr weights = 1 1 1 1
-
-; RED params per traffic class and color (Green / Yellow / Red)
-;[red]
-;tc 0 wred min = 48 40 32
-;tc 0 wred max = 64 64 64
-;tc 0 wred inv prob = 10 10 10
-;tc 0 wred weight = 9 9 9
-
-;tc 1 wred min = 48 40 32
-;tc 1 wred max = 64 64 64
-;tc 1 wred inv prob = 10 10 10
-;tc 1 wred weight = 9 9 9
-
-;tc 2 wred min = 48 40 32
-;tc 2 wred max = 64 64 64
-;tc 2 wred inv prob = 10 10 10
-;tc 2 wred weight = 9 9 9
-
-;tc 3 wred min = 48 40 32
-;tc 3 wred max = 64 64 64
-;tc 3 wred inv prob = 10 10 10
-;tc 3 wred weight = 9 9 9
-
-;tc 4 wred min = 48 40 32
-;tc 4 wred max = 64 64 64
-;tc 4 wred inv prob = 10 10 10
-;tc 4 wred weight = 9 9 9
-
-;tc 5 wred min = 48 40 32
-;tc 5 wred max = 64 64 64
-;tc 5 wred inv prob = 10 10 10
-;tc 5 wred weight = 9 9 9
-
-;tc 6 wred min = 48 40 32
-;tc 6 wred max = 64 64 64
-;tc 6 wred inv prob = 10 10 10
-;tc 6 wred weight = 9 9 9
-
-;tc 7 wred min = 48 40 32
-;tc 7 wred max = 64 64 64
-;tc 7 wred inv prob = 10 10 10
-;tc 7 wred weight = 9 9 9
-
-;tc 8 wred min = 48 40 32
-;tc 8 wred max = 64 64 64
-;tc 8 wred inv prob = 10 10 10
-;tc 8 wred weight = 9 9 9
-
-;tc 9 wred min = 48 40 32
-;tc 9 wred max = 64 64 64
-;tc 9 wred inv prob = 10 10 10
-;tc 9 wred weight = 9 9 9
-
-;tc 10 wred min = 48 40 32
-;tc 10 wred max = 64 64 64
-;tc 10 wred inv prob = 10 10 10
-;tc 10 wred weight = 9 9 9
-
-;tc 11 wred min = 48 40 32
-;tc 11 wred max = 64 64 64
-;tc 11 wred inv prob = 10 10 10
-;tc 11 wred weight = 9 9 9
-
-;tc 12 wred min = 48 40 32
-;tc 12 wred max = 64 64 64
-;tc 12 wred inv prob = 10 10 10
-;tc 12 wred weight = 9 9 9
-
-[pie]
-tc 0 qdelay ref = 15
-tc 0 max burst = 150
-tc 0 update interval = 15
-tc 0 tailq th = 64
-
-tc 1 qdelay ref = 15
-tc 1 max burst = 150
-tc 1 update interval = 15
-tc 1 tailq th = 64
-
-tc 2 qdelay ref = 15
-tc 2 max burst = 150
-tc 2 update interval = 15
-tc 2 tailq th = 64
-
-tc 3 qdelay ref = 15
-tc 3 max burst = 150
-tc 3 update interval = 15
-tc 3 tailq th = 64
-
-tc 4 qdelay ref = 15
-tc 4 max burst = 150
-tc 4 update interval = 15
-tc 4 tailq th = 64
-
-tc 5 qdelay ref = 15
-tc 5 max burst = 150
-tc 5 update interval = 15
-tc 5 tailq th = 64
-
-tc 6 qdelay ref = 15
-tc 6 max burst = 150
-tc 6 update interval = 15
-tc 6 tailq th = 64
-
-tc 7 qdelay ref = 15
-tc 7 max burst = 150
-tc 7 update interval = 15
-tc 7 tailq th = 64
-
-tc 8 qdelay ref = 15
-tc 8 max burst = 150
-tc 8 update interval = 15
-tc 8 tailq th = 64
-
-tc 9 qdelay ref = 15
-tc 9 max burst = 150
-tc 9 update interval = 15
-tc 9 tailq th = 64
-
-tc 10 qdelay ref = 15
-tc 10 max burst = 150
-tc 10 update interval = 15
-tc 10 tailq th = 64
-
-tc 11 qdelay ref = 15
-tc 11 max burst = 150
-tc 11 update interval = 15
-tc 11 tailq th = 64
-
-tc 12 qdelay ref = 15
-tc 12 max burst = 150
-tc 12 update interval = 15
-tc 12 tailq th = 64
+tc 12 wrr weights = 1 1 1 1
\ No newline at end of file
diff --git a/examples/qos_sched/profile_pie.cfg b/examples/qos_sched/profile_pie.cfg
new file mode 100644
index 0000000000..241f748b33
--- /dev/null
+++ b/examples/qos_sched/profile_pie.cfg
@@ -0,0 +1,142 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+[pie]
+tc 0 qdelay ref = 15
+tc 0 max burst = 150
+tc 0 update interval = 15
+tc 0 tailq th = 64
+
+tc 1 qdelay ref = 15
+tc 1 max burst = 150
+tc 1 update interval = 15
+tc 1 tailq th = 64
+
+tc 2 qdelay ref = 15
+tc 2 max burst = 150
+tc 2 update interval = 15
+tc 2 tailq th = 64
+
+tc 3 qdelay ref = 15
+tc 3 max burst = 150
+tc 3 update interval = 15
+tc 3 tailq th = 64
+
+tc 4 qdelay ref = 15
+tc 4 max burst = 150
+tc 4 update interval = 15
+tc 4 tailq th = 64
+
+tc 5 qdelay ref = 15
+tc 5 max burst = 150
+tc 5 update interval = 15
+tc 5 tailq th = 64
+
+tc 6 qdelay ref = 15
+tc 6 max burst = 150
+tc 6 update interval = 15
+tc 6 tailq th = 64
+
+tc 7 qdelay ref = 15
+tc 7 max burst = 150
+tc 7 update interval = 15
+tc 7 tailq th = 64
+
+tc 8 qdelay ref = 15
+tc 8 max burst = 150
+tc 8 update interval = 15
+tc 8 tailq th = 64
+
+tc 9 qdelay ref = 15
+tc 9 max burst = 150
+tc 9 update interval = 15
+tc 9 tailq th = 64
+
+tc 10 qdelay ref = 15
+tc 10 max burst = 150
+tc 10 update interval = 15
+tc 10 tailq th = 64
+
+tc 11 qdelay ref = 15
+tc 11 max burst = 150
+tc 11 update interval = 15
+tc 11 tailq th = 64
+
+tc 12 qdelay ref = 15
+tc 12 max burst = 150
+tc 12 update interval = 15
+tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_red.cfg b/examples/qos_sched/profile_red.cfg
new file mode 100644
index 0000000000..4486d2799e
--- /dev/null
+++ b/examples/qos_sched/profile_red.cfg
@@ -0,0 +1,143 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+; RED params per traffic class and color (Green / Yellow / Red)
+[red]
+tc 0 wred min = 48 40 32
+tc 0 wred max = 64 64 64
+tc 0 wred inv prob = 10 10 10
+tc 0 wred weight = 9 9 9
+
+tc 1 wred min = 48 40 32
+tc 1 wred max = 64 64 64
+tc 1 wred inv prob = 10 10 10
+tc 1 wred weight = 9 9 9
+
+tc 2 wred min = 48 40 32
+tc 2 wred max = 64 64 64
+tc 2 wred inv prob = 10 10 10
+tc 2 wred weight = 9 9 9
+
+tc 3 wred min = 48 40 32
+tc 3 wred max = 64 64 64
+tc 3 wred inv prob = 10 10 10
+tc 3 wred weight = 9 9 9
+
+tc 4 wred min = 48 40 32
+tc 4 wred max = 64 64 64
+tc 4 wred inv prob = 10 10 10
+tc 4 wred weight = 9 9 9
+
+tc 5 wred min = 48 40 32
+tc 5 wred max = 64 64 64
+tc 5 wred inv prob = 10 10 10
+tc 5 wred weight = 9 9 9
+
+tc 6 wred min = 48 40 32
+tc 6 wred max = 64 64 64
+tc 6 wred inv prob = 10 10 10
+tc 6 wred weight = 9 9 9
+
+tc 7 wred min = 48 40 32
+tc 7 wred max = 64 64 64
+tc 7 wred inv prob = 10 10 10
+tc 7 wred weight = 9 9 9
+
+tc 8 wred min = 48 40 32
+tc 8 wred max = 64 64 64
+tc 8 wred inv prob = 10 10 10
+tc 8 wred weight = 9 9 9
+
+tc 9 wred min = 48 40 32
+tc 9 wred max = 64 64 64
+tc 9 wred inv prob = 10 10 10
+tc 9 wred weight = 9 9 9
+
+tc 10 wred min = 48 40 32
+tc 10 wred max = 64 64 64
+tc 10 wred inv prob = 10 10 10
+tc 10 wred weight = 9 9 9
+
+tc 11 wred min = 48 40 32
+tc 11 wred max = 64 64 64
+tc 11 wred inv prob = 10 10 10
+tc 11 wred weight = 9 9 9
+
+tc 12 wred min = 48 40 32
+tc 12 wred max = 64 64 64
+tc 12 wred inv prob = 10 10 10
+tc 12 wred weight = 9 9 9
diff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c
index 599c7e9536..c5fa9e4582 100644
--- a/lib/sched/rte_sched.c
+++ b/lib/sched/rte_sched.c
@@ -81,13 +81,11 @@ struct rte_sched_queue {
struct rte_sched_queue_extra {
struct rte_sched_queue_stats stats;
-#ifdef RTE_SCHED_CMAN
RTE_STD_C11
union {
struct rte_red red;
struct rte_pie pie;
};
-#endif
};
enum grinder_state {
@@ -179,7 +177,6 @@ struct rte_sched_subport {
/* Pipe queues size */
uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
-#ifdef RTE_SCHED_CMAN
bool cman_enabled;
enum rte_sched_cman_mode cman;
@@ -188,7 +185,6 @@ struct rte_sched_subport {
struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];
struct rte_pie_config pie_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
};
-#endif
/* Scheduling loop detection */
uint32_t pipe_loop;
@@ -1084,7 +1080,6 @@ rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports)
rte_free(port);
}
-#ifdef RTE_SCHED_CMAN
static int
rte_sched_red_config(struct rte_sched_port *port,
struct rte_sched_subport *s,
@@ -1166,7 +1161,6 @@ rte_sched_cman_config(struct rte_sched_port *port,
return -EINVAL;
}
-#endif
int
rte_sched_subport_tc_ov_config(struct rte_sched_port *port,
@@ -1285,7 +1279,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
/* TC oversubscription is enabled by default */
s->tc_ov_enabled = 1;
-#ifdef RTE_SCHED_CMAN
if (params->cman_params != NULL) {
s->cman_enabled = true;
status = rte_sched_cman_config(port, s, params, n_subports);
@@ -1297,7 +1290,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
} else {
s->cman_enabled = false;
}
-#endif
/* Scheduling loop detection */
s->pipe_loop = RTE_SCHED_PIPE_INVALID;
@@ -1823,7 +1815,7 @@ rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
uint32_t tc_index = rte_sched_port_pipe_tc(port, qindex);
uint32_t pkt_len = pkt->pkt_len;
@@ -1849,21 +1841,17 @@ static inline void
rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
uint32_t pkt_len = pkt->pkt_len;
qe->stats.n_pkts_dropped += 1;
qe->stats.n_bytes_dropped += pkt_len;
-#ifdef RTE_SCHED_CMAN
if (subport->cman_enabled)
qe->stats.n_pkts_cman_dropped += n_pkts_cman_dropped;
-#endif
}
-#ifdef RTE_SCHED_CMAN
-
static inline int
rte_sched_port_cman_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
@@ -1908,13 +1896,11 @@ static inline void
rte_sched_port_red_set_queue_empty_timestamp(struct rte_sched_port *port,
struct rte_sched_subport *subport, uint32_t qindex)
{
- if (subport->cman_enabled) {
+ if (subport->cman_enabled && subport->cman == RTE_SCHED_CMAN_RED) {
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
- if (subport->cman == RTE_SCHED_CMAN_RED) {
- struct rte_red *red = &qe->red;
+ struct rte_red *red = &qe->red;
- rte_red_mark_queue_empty(red, port->time);
- }
+ rte_red_mark_queue_empty(red, port->time);
}
}
@@ -1933,29 +1919,6 @@ uint32_t qindex, uint32_t pkt_len, uint64_t time) {
}
}
-#else
-
-static inline int rte_sched_port_cman_drop(struct rte_sched_port *port __rte_unused,
- struct rte_sched_subport *subport __rte_unused,
- struct rte_mbuf *pkt __rte_unused,
- uint32_t qindex __rte_unused,
- uint16_t qlen __rte_unused)
-{
- return 0;
-}
-
-#define rte_sched_port_red_set_queue_empty_timestamp(port, subport, qindex)
-
-static inline void
-rte_sched_port_pie_dequeue(struct rte_sched_subport *subport __rte_unused,
- uint32_t qindex __rte_unused,
- uint32_t pkt_len __rte_unused,
- uint64_t time __rte_unused) {
- /* do-nothing when RTE_SCHED_CMAN not defined */
-}
-
-#endif /* RTE_SCHED_CMAN */
-
#ifdef RTE_SCHED_DEBUG
static inline void
--
2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
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Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-11 13:53 [PATCH] sched: enable CMAN at runtime Marcin Danilewicz
2022-05-12 13:10 ` [PATCH v2] " Marcin Danilewicz
2022-05-30 11:19 ` Dumitrescu, Cristian
2022-05-30 14:03 ` Danilewicz, MarcinX
2022-06-02 9:57 ` Danilewicz, MarcinX
2022-05-30 11:35 ` Dumitrescu, Cristian
2022-06-07 10:40 ` Danilewicz, MarcinX
2022-06-08 9:42 ` [PATCH v3] " Marcin Danilewicz
2022-06-08 11:59 ` Dumitrescu, Cristian
2022-06-08 15:29 ` Danilewicz, MarcinX
2022-06-13 9:09 ` [PATCH v4] " Marcin Danilewicz
2022-06-17 11:48 ` Dumitrescu, Cristian
2022-06-20 13:56 ` [PATCH v5] ched: " Marcin Danilewicz
2022-06-20 14:49 ` Dumitrescu, Cristian
2022-06-21 8:20 ` Danilewicz, MarcinX
2022-06-21 8:16 ` [PATCH v6] sched: " Marcin Danilewicz
2022-06-21 13:27 ` Dumitrescu, Cristian
2022-06-22 15:12 ` Danilewicz, MarcinX
2022-07-04 9:19 ` [PATCH v7] " Marcin Danilewicz
2022-07-05 17:05 ` [PATCH v8] " Marcin Danilewicz
2022-07-05 18:00 ` Ajmera, Megha
2022-07-05 22:26 ` Danilewicz, MarcinX
2022-07-06 8:53 ` Singh, Jasvinder
2022-07-07 13:07 ` Danilewicz, MarcinX
2022-07-07 16:28 ` Singh, Jasvinder
2022-07-07 21:22 ` Danilewicz, MarcinX
2022-07-08 13:14 ` [PATCH v9] " Marcin Danilewicz
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