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mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none Received: from CY4PR1201MB0072.namprd12.prod.outlook.com (2603:10b6:910:1b::19) by CY4PR12MB1527.namprd12.prod.outlook.com (2603:10b6:910:5::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3455.26; Thu, 15 Oct 2020 13:45:54 +0000 Received: from CY4PR1201MB0072.namprd12.prod.outlook.com ([fe80::ade4:b300:381d:fe5c]) by CY4PR1201MB0072.namprd12.prod.outlook.com ([fe80::ade4:b300:381d:fe5c%10]) with mapi id 15.20.3477.020; Thu, 15 Oct 2020 13:45:54 +0000 From: Bing Zhao To: NBU-Contact-Thomas Monjalon CC: Ori Kam , "ferruh.yigit@intel.com" , "arybchenko@solarflare.com" , "mdr@ashroe.eu" , "nhorman@tuxdriver.com" , "bernard.iremonger@intel.com" , "beilei.xing@intel.com" , "wenzhuo.lu@intel.com" , "dev@dpdk.org" Thread-Topic: [PATCH v5 2/5] ethdev: add new attributes to hairpin config Thread-Index: AQHWouButZ8nqqRxjUWn5Hue/q0hramYrObw Date: Thu, 15 Oct 2020 13:45:54 +0000 Message-ID: References: <1601511962-21532-1-git-send-email-bingz@nvidia.com> <1602740124-397688-1-git-send-email-bingz@nvidia.com> <1602740124-397688-3-git-send-email-bingz@nvidia.com> <25852134.RkOs9RG3c4@thomas> In-Reply-To: <25852134.RkOs9RG3c4@thomas> Accept-Language: en-US, zh-CN Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: monjalon.net; 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b=PPp7tMLCXyHmyhxwePt3e2tSDxHqFLx4L0MEsP6sRYhtt93oPzqW1GO94hnRwm4YC VX2p3L0Z9zac8pT79mEqIUqX6z3zBTRY9HNU3WQpTMw4CORTMlqWKwPpXT6IdjOGCW kikSNKlTO4YM/lPIpZkSVJV1aoJ7fAXgscnlbb31CR/zUQYFQy4aFnB4TOQptoN45K L6siQ+gdSScbmC5Smy3ay3kTI1YeidP6RL791sC+hN40chxnO6cGjKDtWhJXn5b0O8 R3tTwjhTTHq35CueNqzLf2h2N3w70GTpNHwr5Z4vXyUO7gKDoDMoQ2ETW/xABmVPwc yCdwBfTJcJhaw== Subject: Re: [dpdk-dev] [PATCH v5 2/5] ethdev: add new attributes to hairpin config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Thomas, All comments are addressed and thanks a lot for the reviewing. > -----Original Message----- > From: Thomas Monjalon > Sent: Thursday, October 15, 2020 6:46 PM > To: Bing Zhao > Cc: Ori Kam ; ferruh.yigit@intel.com; > arybchenko@solarflare.com; mdr@ashroe.eu; nhorman@tuxdriver.com; > bernard.iremonger@intel.com; beilei.xing@intel.com; > wenzhuo.lu@intel.com; dev@dpdk.org > Subject: Re: [PATCH v5 2/5] ethdev: add new attributes to hairpin > config >=20 > External email: Use caution opening links or attachments >=20 >=20 > 15/10/2020 07:35, Bing Zhao: > > To support two ports hairpin mode and keep the backward > compatibility > > for the application, two new attribute members of the hairpin > queue > > configuration structure will be added. > > > > `tx_explicit` means if the application itself will insert the TX > part > > flow rules. If not set, PMD will insert the rules implicitly. > > `manual_bind` means if the hairpin TX queue and peer RX queue will > be > > bound automatically during the device start stage. > > > > Different TX and RX queue pairs could have different values, but > it is > > highly recommended that all paired queues between one egress and > its > > peer ingress ports have the same values, in order not to bring any > > chaos to the system. The actual support of these attribute > parameters > > will be checked and decided by the PMD drivers. > > > > In the single port hairpin, if both are zero without any setting, > the > > behavior will remain the same as before. It means that no bind API > > needs to be called and no TX flow rules need to be inserted > manually > > by the application. > > > > Signed-off-by: Bing Zhao > > Acked-by: Ori Kam > > --- > > v4: squash document update and more info for the two new > attributes > > v2: optimize the structure and remove unused macros > > --- >=20 > Acked-by: Thomas Monjalon >=20 > Minor comments below. >=20 > > struct rte_eth_hairpin_conf { > > - uint16_t peer_count; /**< The number of peers. */ > > + uint32_t peer_count:16; /**< The number of peers. */ > > + > > + /** > > + * Explicit TX flow rule mode. One hairpin pair of queues > should have > > + * the same attribute. The actual support depends on the PMD. >=20 > The second sentence should be on a separate line. >=20 > About the third sentence, implementation is always PMD-specific. > PMD will reject the not supported conf, as usual. > I think this comment is not needed in the API description. >=20 > > + * > > + * - When set, the user should be responsible for inserting > the hairpin > > + * TX part flows and removing them. > > + * - When clear, the PMD will try to handle the TX part of > the flows, > > + * e.g., by splitting one flow into two parts. > > + */ > > + uint32_t tx_explicit:1; > > + > > + /** > > + * Manually bind hairpin queues. One hairpin pair of queues > should have > > + * the same attribute. The actual support depends on the PMD. >=20 > Same here >=20 > > + * > > + * - When set, to enable hairpin, the user should call the > hairpin bind > > + * API after all the queues are set up properly and the > ports are > > + * started. Also, the hairpin unbind API should be called > accordingly > > + * before stopping a port that with hairpin configured. > > + * - When clear, the PMD will try to enable the hairpin with > the queues > > + * configured automatically during port start. > > + */ > > + uint32_t manual_bind:1; > > + uint32_t reserved:14; /**< Reserved bits. */ > > struct rte_eth_hairpin_peer peers[RTE_ETH_MAX_HAIRPIN_PEERS]; > > }; >=20 >=20