From: "Kumar, Ravi1" <Ravi1.Kumar@amd.com>
To: Ferruh Yigit <ferruh.yigit@intel.com>,
Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>,
"thomas@monjalon.net" <thomas@monjalon.net>
Cc: "dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH] net/axgbe: fix incorrect cache alignment macro
Date: Mon, 23 Apr 2018 06:32:17 +0000 [thread overview]
Message-ID: <CY4PR12MB1509C13189753706FED830C3AE890@CY4PR12MB1509.namprd12.prod.outlook.com> (raw)
In-Reply-To: <1b2518da-f9ad-5ece-d72d-7af1a1c364e6@intel.com>
>On 4/18/2018 6:17 PM, Ferruh Yigit wrote:
>> On 4/17/2018 9:04 PM, Pavan Nikhilesh wrote:
>>> Due to missing ____cacheline_aligned definition compiler treats it as
>>> a global variable replace it with proper cache alignment macro.
>>>
>>> Fixes: 9e890103267e ("net/axgbe: add Rx/Tx setup")
>>>
>>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>
>>
>> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
>
>Applied to dpdk-next-net/master, thanks.
>
Thanks a lot Ferruh.
Regards,
Ravi
prev parent reply other threads:[~2018-04-23 6:32 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-17 20:04 Pavan Nikhilesh
2018-04-18 17:17 ` Ferruh Yigit
2018-04-18 17:44 ` Ferruh Yigit
2018-04-23 6:32 ` Kumar, Ravi1 [this message]
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