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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: b423b4fc-e5c3-4a57-bdff-08d808424126 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Jun 2020 04:46:32.4647 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: vuD3dPFzcRQAJ199FTbQFWhFpwokoTzUOY258csHXHfaGcXhuZ7fB354i+nN08VjGCEv1+vErNK15vElrq4tYQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1623 Subject: Re: [dpdk-dev] [PATCH v1] net/axgbe: enable IEEE 1588 PTP support for axgbe X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" [AMD Public Use] Acked-by: Somalapuram Amaranath -----Original Message----- From: Sebastian, Selwin Sent: Monday, June 1, 2020 6:28 PM To: dev@dpdk.org Cc: Somalapuram, Amaranath Subject: [PATCH v1] net/axgbe: enable IEEE 1588 PTP support for axgbe From: Selwin Sebastian Add ethdev APIs to support PTP timestamping Signed-off-by: Selwin Sebastian --- drivers/net/axgbe/axgbe_common.h | 8 + drivers/net/axgbe/axgbe_ethdev.c | 327 ++++++++++++++++++++++++++++++- dr= ivers/net/axgbe/axgbe_ethdev.h | 14 ++ drivers/net/axgbe/axgbe_rxtx.c | 11 +- 4 files changed, 358 insertions(+), 2 deletions(-) diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_com= mon.h index f48117180..e0a0b0fbb 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -45,6 +45,7 @@ #endif #define AXGBE_HZ250 +#define NSEC_PER_SEC 1000000000L /* DMA register offsets */ #define DMA_MR0x3000 @@ -491,6 +492,8 @@ #define MAC_TSCR_TSEVNTENA_WIDTH1 #define MAC_TSCR_TSINIT_INDEX2 #define MAC_TSCR_TSINIT_WIDTH1 +#define MAC_TSCR_TSUPDT_INDEX3 +#define MAC_TSCR_TSUPDT_WIDTH1 #define MAC_TSCR_TSIPENA_INDEX11 #define MAC_TSCR_TSIPENA_WIDTH1 #define MAC_TSCR_TSIPV4ENA_INDEX13 @@ -505,6 +508,8 @@ #define MAC_TSCR_TXTSSTSM_WIDTH1 #define MAC_TSSR_TXTSC_INDEX15 #define MAC_TSSR_TXTSC_WIDTH1 +#define MAC_STNUR_ADDSUB_INDEX 31 +#define MAC_STNUR_ADDSUB_WIDTH 1 #define MAC_TXSNR_TXTSSTSMIS_INDEX31 #define MAC_TXSNR_TXTSSTSMIS_WIDTH1 #define MAC_VLANHTR_VLHT_INDEX0 @@ -538,6 +543,7 @@ #define MAC_VR_USERVER_INDEX16 #define MAC_VR_USERVER_WIDTH8 + /* MMC register offsets */ #define MMC_CR0x0800 #define MMC_RISR0x0804 @@ -1170,6 +1176,8 @@ #define RX_CONTEXT_DESC3_TSA_WIDTH1 #define RX_CONTEXT_DESC3_TSD_INDEX6 #define RX_CONTEXT_DESC3_TSD_WIDTH1 +#define RX_CONTEXT_DESC3_PMT_INDEX0 +#define RX_CONTEXT_DESC3_PMT_WIDTH4 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX0 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH1 diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_eth= dev.c index 867058845..18c44404c 100644 --- a/drivers/net/axgbe/axgbe_ethdev.c +++ b/drivers/net/axgbe/axgbe_ethdev.c @@ -8,6 +8,7 @@ #include "axgbe_common.h" #include "axgbe_phy.h" #include "axgbe_regs.h" +#include "rte_time.h" static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); static int et= h_axgbe_dev_uninit(struct rte_eth_dev *eth_dev); @@ -74,6 +75,24 @@ static = void axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, struct rte_eth_txq_info *qinfo); const uint32_t *axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); +static int axgbe_timesync_enable(struct rte_eth_dev *dev); static int +axgbe_timesync_disable(struct rte_eth_dev *dev); static int +axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, +struct timespec *timestamp, uint32_t flags); static int +axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, +struct timespec *timestamp); +static int axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t +delta); static int axgbe_timesync_read_time(struct rte_eth_dev *dev, +struct timespec *timestamp); +static int axgbe_timesync_write_time(struct rte_eth_dev *dev, +const struct timespec *timestamp); +static void axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int s= ec, +unsigned int nsec); +static void axgbe_update_tstamp_addend(struct axgbe_port *pdata, +unsigned int addend); + struct axgbe_xstats { char name[RTE_ETH_XSTATS_NAME_SIZE]; int offset; @@ -214,6 +233,14 @@ static const struct eth_dev_ops axgbe_eth_dev_ops =3D = { .dev_supported_ptypes_get =3D axgbe_dev_supported_ptypes_get, .rx_descriptor_status =3D axgbe_dev_rx_descriptor_status, .tx_descriptor_status =3D axgbe_dev_tx_descriptor_status, +.timesync_enable =3D axgbe_timesync_enable, +.timesync_disable =3D axgbe_timesync_disable, +.timesync_read_rx_timestamp =3D axgbe_timesync_read_rx_timestamp, +.timesync_read_tx_timestamp =3D axgbe_timesync_read_tx_timestamp, +.timesync_adjust_time =3D axgbe_timesync_adjust_time, +.timesync_read_time =3D axgbe_timesync_read_time, +.timesync_write_time =3D axgbe_timesync_write_time, + }; static int axgbe_phy_reset(struct axgbe_port *pdata) @@ -1000,12 +1027,16 = @@ axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev= _info) DEV_RX_OFFLOAD_TCP_CKSUM | DEV_RX_OFFLOAD_JUMBO_FRAME| DEV_RX_OFFLOAD_SCATTER | +PKT_RX_IEEE1588_PTP | DEV_RX_OFFLOAD_KEEP_CRC; dev_info->tx_offload_capa =3D DEV_TX_OFFLOAD_IPV4_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM | -DEV_TX_OFFLOAD_TCP_CKSUM; +DEV_TX_OFFLOAD_TCP_CKSUM | +PKT_TX_IEEE1588_TMST | +DEV_TX_OFFLOAD_MULTI_SEGS; + if (pdata->hw_feat.rss) { dev_info->flow_type_rss_offloads =3D AXGBE_RSS_OFFLOAD; @@ -1255,6 +1286,3= 00 @@ axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) return NULL; } +static void axgbe_update_tstamp_time(struct axgbe_port *pdata, +unsigned int sec, unsigned int nsec, int addsub) { +unsigned int count =3D 100; +uint32_t sub_val =3D 0; +uint32_t sub_val_sec =3D 0xFFFFFFFF; +uint32_t sub_val_nsec =3D 0x3B9ACA00; + +if (addsub) { +if (sec) +sub_val =3D sub_val_sec - (sec - 1); +else +sub_val =3D sec; + +AXGMAC_IOWRITE(pdata, MAC_STSUR, sub_val); +sub_val =3D sub_val_nsec - nsec; +AXGMAC_IOWRITE(pdata, MAC_STNUR, sub_val); +AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 1); +} else { +AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); +AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 0); +AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); +} +AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); +/* Wait for time update to complete */ +while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) +rte_delay_ms(1); +} + +static inline uint64_t +div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) { +*remainder =3D dividend % divisor; +return dividend / divisor; +} + +static inline uint64_t div_u64(uint64_t dividend, uint32_t divisor) { +uint32_t remainder; +return div_u64_rem(dividend, divisor, &remainder); } + +static int axgbe_adjfreq(struct axgbe_port *pdata, int64_t delta) { +uint64_t adjust; +uint32_t addend, diff; +unsigned int neg_adjust =3D 0; + +if (delta < 0) { +neg_adjust =3D 1; +delta =3D -delta; +} +adjust =3D (uint64_t)pdata->tstamp_addend; +adjust *=3D delta; +diff =3D (uint32_t)div_u64(adjust, 1000000000UL); +addend =3D (neg_adjust) ? pdata->tstamp_addend - diff : +pdata->tstamp_addend + diff; +pdata->tstamp_addend =3D addend; +axgbe_update_tstamp_addend(pdata, addend); +return 0; +} + +static int axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t +delta) { +struct axgbe_port *pdata =3D dev->data->dev_private; +struct timespec timestamp_delta; + +axgbe_adjfreq(pdata, delta); +pdata->systime_tc.nsec +=3D delta; + +if (delta < 0) { +delta =3D -delta; +timestamp_delta =3D rte_ns_to_timespec(delta); +axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, +timestamp_delta.tv_nsec, 1); +} else { +timestamp_delta =3D rte_ns_to_timespec(delta); +axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, +timestamp_delta.tv_nsec, 0); +} +return 0; +} + +static int axgbe_timesync_read_time(struct rte_eth_dev *dev, +struct timespec *timestamp) +{ +uint64_t nsec; +struct axgbe_port *pdata =3D dev->data->dev_private; + +nsec =3D AXGMAC_IOREAD(pdata, MAC_STSR); +nsec *=3D NSEC_PER_SEC; +nsec +=3D AXGMAC_IOREAD(pdata, MAC_STNR); +*timestamp =3D rte_ns_to_timespec(nsec); +return 0; +} +static int axgbe_timesync_write_time(struct rte_eth_dev *dev, + const struct timespec *timestamp) { +unsigned int count =3D 100; +struct axgbe_port *pdata =3D dev->data->dev_private; + +AXGMAC_IOWRITE(pdata, MAC_STSUR, timestamp->tv_sec); +AXGMAC_IOWRITE(pdata, MAC_STNUR, timestamp->tv_nsec); +AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); +/* Wait for time update to complete */ +while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) +rte_delay_ms(1); +if (!count) +PMD_DRV_LOG(ERR, "Timed out update timestamp\n"); +return 0; +} + +static void axgbe_update_tstamp_addend(struct axgbe_port *pdata, +uint32_t addend) +{ +unsigned int count =3D 100; + +AXGMAC_IOWRITE(pdata, MAC_TSAR, addend); +AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); + +/* Wait for addend update to complete */ +while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) +rte_delay_ms(1); +if (!count) +PMD_DRV_LOG(ERR, "Timed out updating timestamp addend register\n"); } + +static void axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int s= ec, +unsigned int nsec) +{ +unsigned int count =3D 100; + +/*System Time Sec Update*/ +AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); +/*System Time nanoSec Update*/ +AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); +/*Initialize Timestamp*/ +AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); + +/* Wait for time update to complete */ +while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) +rte_delay_ms(1); +if (!count) +PMD_DRV_LOG(ERR, "Timed out initializing timestamp\n"); } + +static int +axgbe_timesync_enable(struct rte_eth_dev *dev) { +struct axgbe_port *pdata =3D dev->data->dev_private; +unsigned int mac_tscr =3D 0; +uint64_t dividend; +struct timespec timestamp; +uint64_t nsec; + +/* Set one nano-second accuracy */ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); + +/* Set fine timestamp update */ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); + +/* Overwrite earlier timestamps */ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); + +AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); + +/* Enabling processing of ptp over eth pkt */ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); +/* Enable timestamp for all pkts*/ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); + +/* enabling timestamp */ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); +AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); + +/* Exit if timestamping is not enabled */ +if (!AXGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) { +PMD_DRV_LOG(ERR, "Exiting as timestamp is not enabled\n"); +return 0; +} + +/* Sub-second Increment Value*/ +AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, AXGBE_TSTAMP_SSINC); +/* Sub-nanosecond Increment Value */ +AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, AXGBE_TSTAMP_SNSINC); + +pdata->ptpclk_rate =3D AXGBE_V2_PTP_CLOCK_FREQ; +dividend =3D 50000000; +dividend <<=3D 32; +pdata->tstamp_addend =3D div_u64(dividend, pdata->ptpclk_rate); + +axgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); +axgbe_set_tstamp_time(pdata, 0, 0); + +/* Initialize the timecounter */ +memset(&pdata->systime_tc, 0, sizeof(struct rte_timecounter)); + +pdata->systime_tc.cc_mask =3D AXGBE_CYCLECOUNTER_MASK; +pdata->systime_tc.cc_shift =3D 0; +pdata->systime_tc.nsec_mask =3D 0; + +PMD_DRV_LOG(DEBUG, "Intializing system time counter with realtime\n"); + +/* Updating the counter once with clock real time */ +clock_gettime(CLOCK_REALTIME, ×tamp); +nsec =3D rte_timespec_to_ns(×tamp); +nsec =3D rte_timecounter_update(&pdata->systime_tc, nsec); +axgbe_set_tstamp_time(pdata, timestamp.tv_sec, timestamp.tv_nsec); +return 0; +} + +static int +axgbe_timesync_disable(struct rte_eth_dev *dev) { +struct axgbe_port *pdata =3D dev->data->dev_private; +unsigned int mac_tscr =3D 0; + +/*disable timestamp for all pkts*/ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 0); +/*disable the addened register*/ +AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 0); +/* disable timestamp update */ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 0); +/*disable time stamp*/ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 0); +return 0; +} + +static int +axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, +struct timespec *timestamp, uint32_t flags) { +uint64_t nsec =3D 0; +volatile union axgbe_rx_desc *desc; +uint16_t idx, pmt; +struct axgbe_rx_queue *rxq =3D *dev->data->rx_queues; + +idx =3D AXGBE_GET_DESC_IDX(rxq, rxq->cur); +desc =3D &rxq->desc[idx]; + +while (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN)) +rte_delay_ms(1); +if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CTXT)) { +if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_CONTEXT_DESC3, TSA) +&& !AXGMAC_GET_BITS_LE(desc->write.desc3, +RX_CONTEXT_DESC3, TSD)) { +pmt =3D AXGMAC_GET_BITS_LE(desc->write.desc3, +RX_CONTEXT_DESC3, PMT); +nsec =3D rte_le_to_cpu_32(desc->write.desc1); +nsec *=3D NSEC_PER_SEC; +nsec +=3D rte_le_to_cpu_32(desc->write.desc0); +if (nsec !=3D 0xffffffffffffffffULL) { +if (pmt =3D=3D 0x01) +*timestamp =3D rte_ns_to_timespec(nsec); +PMD_DRV_LOG(DEBUG, "flags =3D 0x%x nsec =3D %ld\n", +flags, nsec); +} +} +} + +return 0; +} + +static int +axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, +struct timespec *timestamp) +{ +uint64_t nsec; +struct axgbe_port *pdata =3D dev->data->dev_private; +unsigned int tx_snr, tx_ssr; + +rte_delay_us(5); +if (pdata->vdata->tx_tstamp_workaround) { +tx_snr =3D AXGMAC_IOREAD(pdata, MAC_TXSNR); +tx_ssr =3D AXGMAC_IOREAD(pdata, MAC_TXSSR); + +} else { +tx_ssr =3D AXGMAC_IOREAD(pdata, MAC_TXSSR); +tx_snr =3D AXGMAC_IOREAD(pdata, MAC_TXSNR); +} +if (AXGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) { +PMD_DRV_LOG(DEBUG, "Waiting for TXTSSTSMIS\n"); +return 0; +} +nsec =3D tx_ssr; +nsec *=3D NSEC_PER_SEC; +nsec +=3D tx_snr; +PMD_DRV_LOG(DEBUG, "nsec =3D %ld tx_ssr =3D %d tx_snr =3D %d\n", +nsec, tx_ssr, tx_snr); +*timestamp =3D rte_ns_to_timespec(nsec); +return 0; +} + static void axgbe_get_all_hw_features(struct axgbe_port *pdata) { unsigned int mac_hfr0, mac_hfr1, mac_hfr2; diff --git a/drivers/net/axgbe/= axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h index f10ec4a40..8a6bbbb22 100644 --- a/drivers/net/axgbe/axgbe_ethdev.h +++ b/drivers/net/axgbe/axgbe_ethdev.h @@ -9,6 +9,7 @@ #include #include #include "axgbe_common.h" +#include "rte_time.h" #define IRQ0xff #define VLAN_HLEN4 @@ -63,6 +64,13 @@ #define AXGBE_V2_DMA_CLOCK_FREQ500000000 #define AXGBE_V2_PTP_CLOCK_FREQ125000000 +/* Timestamp support - values based on 50MHz PTP clock + * 50MHz =3D> 20 nsec + */ +#define AXGBE_TSTAMP_SSINC 20 +#define AXGBE_TSTAMP_SNSINC 0 +#define AXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL + #define AXGMAC_FIFO_MIN_ALLOC2048 #define AXGMAC_FIFO_UNIT256 #define AXGMAC_FIFO_ALIGN(_x) \ @@ -644,6 +652,12 @@ struct axgbe_port { unsigned int hash_table_count; unsigned int uc_hash_mac_addr; unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE]; + +/* For IEEE1588 PTP */ +struct rte_timecounter systime_tc; +struct rte_timecounter tx_tstamp; +unsigned int tstamp_addend; + }; void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if); diff --git a= /drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c index 30c4= 67db7..19195109b 100644 --- a/drivers/net/axgbe/axgbe_rxtx.c +++ b/drivers/net/axgbe/axgbe_rxtx.c @@ -275,6 +275,9 @@ axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pk= ts, /* Get the RSS hash */ if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV)) mbuf->hash.rss =3D rte_le_to_cpu_32(desc->write.desc1); +/* Indicate if a Context Descriptor is next */ +if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CDA)) +mbuf->ol_flags |=3D PKT_RX_IEEE1588_PTP; pkt_len =3D AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, PL) - rxq->crc_len; /* Mbuf populate */ @@ -487,6 +490,7 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, u= int16_t queue_idx, struct axgbe_tx_queue *txq; unsigned int tsize; const struct rte_memzone *tz; +struct rte_eth_dev_data *dev_data; tx_desc =3D nb_desc; pdata =3D dev->data->dev_private; @@ -507,6 +511,7 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, u= int16_t queue_idx, return -ENOMEM; txq->pdata =3D pdata; +dev_data =3D pdata->eth_dev->data; txq->nb_desc =3D tx_desc; txq->free_thresh =3D tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh : AXGBE_TX_FREE_THRESH; @@ -518,7 +523,7 @@ int ax= gbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, if (txq->nb_desc % txq->free_thresh !=3D 0) txq->vector_disable =3D 1; -if (tx_conf->offloads !=3D 0) +if ((tx_conf->offloads !=3D 0) || dev_data->dev_conf.txmode.offloads) txq->vector_disable =3D 1; /* Allocate TX ring hardware descriptors */ @@ -722,6 +727,10 @@ static in= t axgbe_xmit_hw(struct axgbe_tx_queue *txq, /* Total msg length to transmit */ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FL, mbuf->pkt_len); +/* Timestamp enablement check */ +if (mbuf->ol_flags & PKT_TX_IEEE1588_TMST) +AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, TTSE, 1); +rte_wmb(); /* Mark it as First and Last Descriptor */ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FD, 1); AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, LD, 1); -- 2.17.1