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SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: kfZ/Zhg9BZS7rEIx3iTTYakpZbC544y54cECc0i9/c71vs4rviwhPAFH2q7zp3dNMFi1Y9PlrwwjW87Me+DNyYKeZksqPfmu3kQnLDwbINrAxgdqsOzETSoptsVJSnTk6d6BtlZIJpSaZOTynNWdALzfI97Se2GPBeWoeLDefN2gi8qKn20KafV2rfOhApZ/Oumk9qCqbL05y+NrXlmHJThuekfJWRXRjgBy/ja2TituFqxx5dsvisVOmwGY7b6QtSiSGc5D0AQs/1Wkynn/doMLyOfdwr4iB3ZdInxMQ3xioBVNuNP9RkEOxbmzEmn2a8pNljQlhedC+Vy3P8Yg377/+znUoCiLVp1F2jVZeArbMf6suYQ501akZT2lILxQh0/FmwknOYCpuYQcx/m/DyiP7ASZKnXueihu41c7JJA= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: c5fcf035-87ce-4199-d0ac-08d6be43f9c8 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Apr 2019 06:07:28.0996 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1801MB1829 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-11_04:, , signatures=0 Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 11 Apr 2019 06:08:48 -0000 Hi Yongseok, >-----Original Message----- >From: Yongseok Koh >Sent: Wednesday, April 10, 2019 11:08 PM >To: Pavan Nikhilesh Bhagavatula >Cc: Thomas Monjalon ; dev ; Jerin >Jacob Kollanukkaran ; jerinjacobk@gmail.com >Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support >machine specific flags > >External Email > >---------------------------------------------------------------------- > >> On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote: >> >> From: Pavan Nikhilesh >> >> Currently, RTE_* flags are set based on the implementer ID but there >> might be some micro arch specific differences from the same vendor eg. >> CACHE_LINESIZE. Add support to set micro arch specific flags. >> >> Signed-off-by: Pavan Nikhilesh >> Signed-off-by: Jerin Jacob >> --- >> config/arm/meson.build | 56 ++++++++++++++++++++++++------------------ >> 1 file changed, 32 insertions(+), 24 deletions(-) >> >> diff --git a/config/arm/meson.build b/config/arm/meson.build index >> 170a4981a..24bce2b39 100644 >> --- a/config/arm/meson.build >> +++ b/config/arm/meson.build >> @@ -7,25 +7,6 @@ march_opt =3D '-march=3D@0@'.format(machine) >> >> arm_force_native_march =3D false >> >> -machine_args_generic =3D [ >> - ['default', ['-march=3Darmv8-a+crc+crypto']], >> - ['native', ['-march=3Dnative']], >> - ['0xd03', ['-mcpu=3Dcortex-a53']], >> - ['0xd04', ['-mcpu=3Dcortex-a35']], >> - ['0xd05', ['-mcpu=3Dcortex-a55']], >> - ['0xd07', ['-mcpu=3Dcortex-a57']], >> - ['0xd08', ['-mcpu=3Dcortex-a72']], >> - ['0xd09', ['-mcpu=3Dcortex-a73']], >> - ['0xd0a', ['-mcpu=3Dcortex-a75']], >> - ['0xd0b', ['-mcpu=3Dcortex-a76']], >> -] >> -machine_args_cavium =3D [ >> - ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >> - ['native', ['-march=3Dnative']], >> - ['0xa1', ['-mcpu=3Dthunderxt88']], >> - ['0xa2', ['-mcpu=3Dthunderxt81']], >> - ['0xa3', ['-mcpu=3Dthunderxt83']]] >> - >> flags_common_default =3D [ >> # Accelarate rte_memcpy. Be sure to run unit test >(memcpy_perf_autotest) >> # to determine the best threshold in code. Refer to notes in source >> file @@ -52,12 +33,10 @@ flags_generic =3D [ >> ['RTE_USE_C11_MEM_MODEL', true], >> ['RTE_CACHE_LINE_SIZE', 128]] >> flags_cavium =3D [ >> - ['RTE_MACHINE', '"thunderx"'], >> ['RTE_CACHE_LINE_SIZE', 128], >> ['RTE_MAX_NUMA_NODES', 2], >> ['RTE_MAX_LCORE', 96], >> - ['RTE_MAX_VFIO_GROUPS', 128], >> - ['RTE_USE_C11_MEM_MODEL', false]] >> + ['RTE_MAX_VFIO_GROUPS', 128]] >> flags_dpaa =3D [ >> ['RTE_MACHINE', '"dpaa"'], >> ['RTE_USE_C11_MEM_MODEL', true], >> @@ -71,6 +50,27 @@ flags_dpaa2 =3D [ >> ['RTE_MAX_NUMA_NODES', 1], >> ['RTE_MAX_LCORE', 16], >> ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] >> +flags_default_extra =3D [] >> +flags_thunderx_extra =3D [ >> + ['RTE_MACHINE', '"thunderx"'], >> + ['RTE_USE_C11_MEM_MODEL', false]] >> + >> +machine_args_generic =3D [ >> + ['default', ['-march=3Darmv8-a+crc+crypto']], >> + ['native', ['-march=3Dnative']], >> + ['0xd03', ['-mcpu=3Dcortex-a53']], >> + ['0xd04', ['-mcpu=3Dcortex-a35']], >> + ['0xd07', ['-mcpu=3Dcortex-a57']], >> + ['0xd08', ['-mcpu=3Dcortex-a72']], >> + ['0xd09', ['-mcpu=3Dcortex-a73']], >> + ['0xd0a', ['-mcpu=3Dcortex-a75']]] >> + >> +machine_args_cavium =3D [ >> + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >> + ['native', ['-march=3Dnative']], >> + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], >> + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], >> + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >> >> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page >> G7-5321) impl_generic =3D ['Generic armv8', flags_generic, >> machine_args_generic] @@ -157,8 +157,16 @@ else >> endif >> foreach marg: machine[2] >> if marg[0] =3D=3D impl_pn >> - foreach f: marg[1] >> - machine_args +=3D f >> + foreach flag: marg[1] >> + if cc.has_argument(flag) >> + machine_args +=3D flag >> + endif >> + endforeach >> + # Apply any extra machine specific flags. >> + foreach flag: marg.get(2, flags_default_extra) >> + if flag.length() > 0 >> + dpdk_conf.set(flag[0], flag[1]) >> + endif > >Let me continue the discussion from v7 here. >Seems I wan't clear enough. > >Let me take an example. If the host is thunderx2 (0xaf) and compiler is ol= der >than v7, flags_thunderx2_extra isn't set. This means, for example, >RTE_CACHE_LINE_SIZE will still be 128. Is that what you want? >RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you might >want to set it regardless of gcc version. You could skip setting -mcpu wit= h setting >the extra flags. > Thanks for the detailed explanation. I think since we have the check to skip mcpu flag when cc doesn't support i= t (cc.has_argument(flag)) It will be safe to remove=20 ` # Primary part number based mcpu flags are supported # for gcc versions > 7 if cc.version().version_compare( '<7.0') or cmd_output.length() =3D=3D 0 if not meson.is_cross_build() and arm_force_native_march = =3D=3D true impl_pn =3D 'native' else impl_pn =3D 'default' endif endif ` The command output check can also be removed as it is handled when calling = the command script itself. Thoughts? PS. I think the safest way to set CACHELINE_SIZE is to read the cache type = register[1] but sadly only few latest kernels=20 have the support through sysfs (/sys/devices/system/cpu/cpu0/cache/index0/c= oherency_line_size)=20 >Thoughts? > >Thanks, >Yongseok > > > Regards, Pavan. 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SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: kfZ/Zhg9BZS7rEIx3iTTYakpZbC544y54cECc0i9/c71vs4rviwhPAFH2q7zp3dNMFi1Y9PlrwwjW87Me+DNyYKeZksqPfmu3kQnLDwbINrAxgdqsOzETSoptsVJSnTk6d6BtlZIJpSaZOTynNWdALzfI97Se2GPBeWoeLDefN2gi8qKn20KafV2rfOhApZ/Oumk9qCqbL05y+NrXlmHJThuekfJWRXRjgBy/ja2TituFqxx5dsvisVOmwGY7b6QtSiSGc5D0AQs/1Wkynn/doMLyOfdwr4iB3ZdInxMQ3xioBVNuNP9RkEOxbmzEmn2a8pNljQlhedC+Vy3P8Yg377/+znUoCiLVp1F2jVZeArbMf6suYQ501akZT2lILxQh0/FmwknOYCpuYQcx/m/DyiP7ASZKnXueihu41c7JJA= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: c5fcf035-87ce-4199-d0ac-08d6be43f9c8 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Apr 2019 06:07:28.0996 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1801MB1829 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-11_04:, , signatures=0 Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190411060728.FZUZzRbDW4cbyH5kPrkEEVXo1irhe9YOyPOo-YjuJso@z> Hi Yongseok, >-----Original Message----- >From: Yongseok Koh >Sent: Wednesday, April 10, 2019 11:08 PM >To: Pavan Nikhilesh Bhagavatula >Cc: Thomas Monjalon ; dev ; Jerin >Jacob Kollanukkaran ; jerinjacobk@gmail.com >Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support >machine specific flags > >External Email > >---------------------------------------------------------------------- > >> On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote: >> >> From: Pavan Nikhilesh >> >> Currently, RTE_* flags are set based on the implementer ID but there >> might be some micro arch specific differences from the same vendor eg. >> CACHE_LINESIZE. Add support to set micro arch specific flags. >> >> Signed-off-by: Pavan Nikhilesh >> Signed-off-by: Jerin Jacob >> --- >> config/arm/meson.build | 56 ++++++++++++++++++++++++------------------ >> 1 file changed, 32 insertions(+), 24 deletions(-) >> >> diff --git a/config/arm/meson.build b/config/arm/meson.build index >> 170a4981a..24bce2b39 100644 >> --- a/config/arm/meson.build >> +++ b/config/arm/meson.build >> @@ -7,25 +7,6 @@ march_opt =3D '-march=3D@0@'.format(machine) >> >> arm_force_native_march =3D false >> >> -machine_args_generic =3D [ >> - ['default', ['-march=3Darmv8-a+crc+crypto']], >> - ['native', ['-march=3Dnative']], >> - ['0xd03', ['-mcpu=3Dcortex-a53']], >> - ['0xd04', ['-mcpu=3Dcortex-a35']], >> - ['0xd05', ['-mcpu=3Dcortex-a55']], >> - ['0xd07', ['-mcpu=3Dcortex-a57']], >> - ['0xd08', ['-mcpu=3Dcortex-a72']], >> - ['0xd09', ['-mcpu=3Dcortex-a73']], >> - ['0xd0a', ['-mcpu=3Dcortex-a75']], >> - ['0xd0b', ['-mcpu=3Dcortex-a76']], >> -] >> -machine_args_cavium =3D [ >> - ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >> - ['native', ['-march=3Dnative']], >> - ['0xa1', ['-mcpu=3Dthunderxt88']], >> - ['0xa2', ['-mcpu=3Dthunderxt81']], >> - ['0xa3', ['-mcpu=3Dthunderxt83']]] >> - >> flags_common_default =3D [ >> # Accelarate rte_memcpy. Be sure to run unit test >(memcpy_perf_autotest) >> # to determine the best threshold in code. Refer to notes in source >> file @@ -52,12 +33,10 @@ flags_generic =3D [ >> ['RTE_USE_C11_MEM_MODEL', true], >> ['RTE_CACHE_LINE_SIZE', 128]] >> flags_cavium =3D [ >> - ['RTE_MACHINE', '"thunderx"'], >> ['RTE_CACHE_LINE_SIZE', 128], >> ['RTE_MAX_NUMA_NODES', 2], >> ['RTE_MAX_LCORE', 96], >> - ['RTE_MAX_VFIO_GROUPS', 128], >> - ['RTE_USE_C11_MEM_MODEL', false]] >> + ['RTE_MAX_VFIO_GROUPS', 128]] >> flags_dpaa =3D [ >> ['RTE_MACHINE', '"dpaa"'], >> ['RTE_USE_C11_MEM_MODEL', true], >> @@ -71,6 +50,27 @@ flags_dpaa2 =3D [ >> ['RTE_MAX_NUMA_NODES', 1], >> ['RTE_MAX_LCORE', 16], >> ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] >> +flags_default_extra =3D [] >> +flags_thunderx_extra =3D [ >> + ['RTE_MACHINE', '"thunderx"'], >> + ['RTE_USE_C11_MEM_MODEL', false]] >> + >> +machine_args_generic =3D [ >> + ['default', ['-march=3Darmv8-a+crc+crypto']], >> + ['native', ['-march=3Dnative']], >> + ['0xd03', ['-mcpu=3Dcortex-a53']], >> + ['0xd04', ['-mcpu=3Dcortex-a35']], >> + ['0xd07', ['-mcpu=3Dcortex-a57']], >> + ['0xd08', ['-mcpu=3Dcortex-a72']], >> + ['0xd09', ['-mcpu=3Dcortex-a73']], >> + ['0xd0a', ['-mcpu=3Dcortex-a75']]] >> + >> +machine_args_cavium =3D [ >> + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >> + ['native', ['-march=3Dnative']], >> + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], >> + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], >> + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >> >> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page >> G7-5321) impl_generic =3D ['Generic armv8', flags_generic, >> machine_args_generic] @@ -157,8 +157,16 @@ else >> endif >> foreach marg: machine[2] >> if marg[0] =3D=3D impl_pn >> - foreach f: marg[1] >> - machine_args +=3D f >> + foreach flag: marg[1] >> + if cc.has_argument(flag) >> + machine_args +=3D flag >> + endif >> + endforeach >> + # Apply any extra machine specific flags. >> + foreach flag: marg.get(2, flags_default_extra) >> + if flag.length() > 0 >> + dpdk_conf.set(flag[0], flag[1]) >> + endif > >Let me continue the discussion from v7 here. >Seems I wan't clear enough. > >Let me take an example. If the host is thunderx2 (0xaf) and compiler is ol= der >than v7, flags_thunderx2_extra isn't set. This means, for example, >RTE_CACHE_LINE_SIZE will still be 128. Is that what you want? >RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you might >want to set it regardless of gcc version. You could skip setting -mcpu wit= h setting >the extra flags. > Thanks for the detailed explanation. I think since we have the check to skip mcpu flag when cc doesn't support i= t (cc.has_argument(flag)) It will be safe to remove=20 ` # Primary part number based mcpu flags are supported # for gcc versions > 7 if cc.version().version_compare( '<7.0') or cmd_output.length() =3D=3D 0 if not meson.is_cross_build() and arm_force_native_march = =3D=3D true impl_pn =3D 'native' else impl_pn =3D 'default' endif endif ` The command output check can also be removed as it is handled when calling = the command script itself. Thoughts? PS. I think the safest way to set CACHELINE_SIZE is to read the cache type = register[1] but sadly only few latest kernels=20 have the support through sysfs (/sys/devices/system/cpu/cpu0/cache/index0/c= oherency_line_size)=20 >Thoughts? > >Thanks, >Yongseok > > > Regards, Pavan.