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Sat, 27 Jul 2019 11:51:51 +0000 Received: from CY4PR1801MB1863.namprd18.prod.outlook.com ([fe80::1859:6ecd:9898:f96c]) by CY4PR1801MB1863.namprd18.prod.outlook.com ([fe80::1859:6ecd:9898:f96c%7]) with mapi id 15.20.2115.005; Sat, 27 Jul 2019 11:51:51 +0000 From: Pavan Nikhilesh Bhagavatula To: Jerin Jacob Kollanukkaran , "dev@dpdk.org" , Jerin Jacob Kollanukkaran , "Nithin Kumar Dabilpuram" , Vamsi Krishna Attunuru CC: "thomas@monjalon.net" Thread-Topic: [dpdk-dev] [PATCH] common/octeontx2: fix to prevent STP instruction fissure Thread-Index: AdVEcZplvFgVb1Y3QJGzV6xFpFz3bg== Date: Sat, 27 Jul 2019 11:51:50 +0000 Message-ID: Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [183.82.16.194] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: a23c440f-9e48-4eeb-674c-08d71288d023 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328)(7193020); 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: a23c440f-9e48-4eeb-674c-08d71288d023 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Jul 2019 11:51:51.1768 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pbhagavatula@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1801MB1925 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-07-27_09:2019-07-26,2019-07-27 signatures=0 Subject: Re: [dpdk-dev] [PATCH] common/octeontx2: fix to prevent STP instruction fissure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >-----Original Message----- >From: dev On Behalf Of jerinj@marvell.com >Sent: Friday, July 26, 2019 10:55 AM >To: dev@dpdk.org; Jerin Jacob Kollanukkaran ; >Nithin Kumar Dabilpuram ; Vamsi Krishna >Attunuru >Cc: thomas@monjalon.net >Subject: [EXT] [dpdk-dev] [PATCH] common/octeontx2: fix to prevent >STP instruction fissure >From: Jerin Jacob > >OTX2 AP core can sometimes fissure STP instructions when it is more >optimal to send such writes into the pipeline as 2 separate >instructions. However registers should be excluded from such >optimization. This commit ensures that no CSR write is ever fissured >by introducing zero cost workaround by setting STP pre-index by zero to >make sure OTX2 AP core prevent fissure. > >Fixes: 8a4f835971f5 ("common/octeontx2: add IO handling APIs") > >Signed-off-by: Jerin Jacob Acked-by: Pavan Nikhilesh >--- > drivers/common/octeontx2/otx2_io_arm64.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > >diff --git a/drivers/common/octeontx2/otx2_io_arm64.h >b/drivers/common/octeontx2/otx2_io_arm64.h >index 468243c04..7e45329b3 100644 >--- a/drivers/common/octeontx2/otx2_io_arm64.h >+++ b/drivers/common/octeontx2/otx2_io_arm64.h >@@ -14,7 +14,7 @@ > > #define otx2_store_pair(val0, val1, addr) ({ \ > asm volatile( \ >- "stp %x[x0], %x[x1], [%x[p1]]" \ >+ "stp %x[x0], %x[x1], [%x[p1],#0]!" \ > ::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \ > ); }) > >-- >2.22.0