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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 640bb14f-5e3f-47fb-4e43-08d76c43e2ac X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Nov 2019 16:25:11.6546 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: t+5vqBnhIf2jW72UFGnxkF7Vb7MQEhdO1kbANJtQ15x9KFFYbA1ekELsqNg1diCJIAae5Hjq90aEEPAQt9LIKg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB4044 Subject: Re: [dpdk-dev] [PATCH] net/mlx5: fix Tx doorbell write memory barrier X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, > -----Original Message----- > From: Viacheslav Ovsiienko > Sent: Friday, November 15, 2019 1:35 PM > To: dev@dpdk.org > Cc: Matan Azrad ; Raslan Darawsheh > ; Ori Kam > Subject: [PATCH] net/mlx5: fix Tx doorbell write memory barrier >=20 > As the result of testing it was found that some hosts have > the performance penalty imposed by required write memory barrier > after doorbell writing. Before 19.08 release there was some > heuristics to decide whether write memory barrier should be > performed. For the bursts of recommended size (or multiple) > it was supposed there were some extra ongoing packets in the > next burst and write memory barrier may be skipped (supposed > to be performed in the next burst, at least after descriptor > writing). >=20 > This patch restores that behaviour, the devargs tx_db_nc=3D2 > must be specified to engage this performance tuning feature. >=20 > Fixes: 8409a28573d3 ("net/mlx5: control transmit doorbell register mappin= g") >=20 > Signed-off-by: Viacheslav Ovsiienko > --- Patch applied to next-net-mlx, Kindest regards, Raslan Darawsheh