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X-Microsoft-Antispam-Message-Info: N2V2yiMvLqvxpsaRWkPyr0aLQvFc8B/Hka+KpiwbckZ58awKpxHDTb/w9XJhhAU2gLGDrbYuPNsLG+v5jPXWgE4JTEsbTTJTbjbZJpZCwiv0RbVGgSTawXU4JV6x3YJtcqXXQbPkLLF79uR//XkSGHSMVX6+/NS65ZWiPO1QcF5Tznm3YCrtm7uNLHUpa2dA6lwd98ImoUCPCsLQSRCujxG03cWGSgLzG4yd6oEIVbYVkJZTC+6DZIFy6xo49sAcnZ2RpATuxXZcD/u8NzCpaXUrh1p4LWgdxoQcNR1fm2kAZ/I6gBEjqqww33REt54m6EQqLbuar7h3YXmiqh9PG/fajQvDfGxq1LyMuruQfHjxv0+KfPVpJiX1kRmwO2Xf+I05HOVYJz5F3/E760luqw== X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2020 18:22:47.0600 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df48d0c5-1a69-402d-8fdc-08d829b53d89 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT034.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0801MB1687 Subject: Re: [dpdk-dev] [PATCH v8 1/3] doc: add optimizations using C11 atomic built-ins X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > Subject: [PATCH v8 1/3] doc: add optimizations using C11 atomic built-ins >=20 > Add information about possible optimizations using C11 atomic built-ins. >=20 > Signed-off-by: Phil Yang > Signed-off-by: Honnappa Nagarahalli Thanks for the changes, they look good now. David wanted to change 'built-ins' to 'builtins', otherwise Reviewed-by: Honnappa Nagarahalli > --- > doc/guides/prog_guide/writing_efficient_code.rst | 59 > +++++++++++++++++++++++- > 1 file changed, 58 insertions(+), 1 deletion(-) >=20 > diff --git a/doc/guides/prog_guide/writing_efficient_code.rst > b/doc/guides/prog_guide/writing_efficient_code.rst > index 849f63e..53a1ca1 100644 > --- a/doc/guides/prog_guide/writing_efficient_code.rst > +++ b/doc/guides/prog_guide/writing_efficient_code.rst > @@ -167,7 +167,13 @@ but with the added cost of lower throughput. > Locks and Atomic Operations > --------------------------- >=20 > -Atomic operations imply a lock prefix before the instruction, > +This section describes some key considerations when using locks and > +atomic operations in the DPDK environment. > + > +Locks > +~~~~~ > + > +On x86, atomic operations imply a lock prefix before the instruction, > causing the processor's LOCK# signal to be asserted during execution of = the > following instruction. > This has a big impact on performance in a multicore environment. >=20 > @@ -176,6 +182,57 @@ It can often be replaced by other solutions like per= - > lcore variables. > Also, some locking techniques are more efficient than others. > For instance, the Read-Copy-Update (RCU) algorithm can frequently replac= e > simple rwlocks. >=20 > +Atomic Operations: Use C11 Atomic Built-ins > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > + > +DPDK generic rte_atomic operations are implemented by __sync built-ins. > +These __sync built-ins result in full barriers on aarch64, which are > +unnecessary in many use cases. They can be replaced by __atomic > +built-ins that conform to the C11 memory model and provide finer memory > order control. > + > +So replacing the rte_atomic operations with __atomic built-ins might > +improve performance for aarch64 machines. > + > +Some typical optimization cases are listed below: > + > +Atomicity > +^^^^^^^^^ > + > +Some use cases require atomicity alone, the ordering of the memory > +operations does not matter. For example, the packet statistics counters > +need to be incremented atomically but do not need any particular memory > ordering. > +So, RELAXED memory ordering is sufficient. > + > +One-way Barrier > +^^^^^^^^^^^^^^^ > + > +Some use cases allow for memory reordering in one way while requiring > +memory ordering in the other direction. > + > +For example, the memory operations before the spinlock lock are allowed > +to move to the critical section, but the memory operations in the > +critical section are not allowed to move above the lock. In this case, > +the full memory barrier in the compare-and-swap operation can be replace= d > with ACQUIRE memory order. > +On the other hand, the memory operations after the spinlock unlock are > +allowed to move to the critical section, but the memory operations in > +the critical section are not allowed to move below the unlock. So the > +full barrier in the store operation can use RELEASE memory order. > + > +Reader-Writer Concurrency > +^^^^^^^^^^^^^^^^^^^^^^^^^ > + > +Lock-free reader-writer concurrency is one of the common use cases in DP= DK. > + > +The payload or the data that the writer wants to communicate to the > +reader, can be written with RELAXED memory order. However, the guard > +variable should be written with RELEASE memory order. This ensures that > +the store to guard variable is observable only after the store to payloa= d is > observable. > + > +Correspondingly, on the reader side, the guard variable should be read > +with ACQUIRE memory order. The payload or the data the writer > +communicated, can be read with RELAXED memory order. This ensures that, > +if the store to guard variable is observable, the store to payload is al= so > observable. > + > Coding Considerations > --------------------- >=20 > -- > 2.7.4