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Tue, 12 Feb 2019 08:06:17 +0000 From: "Phil Yang (Arm Technology China)" To: Pavan Nikhilesh Bhagavatula , "jerinj@marvell.com" , "Gavin Hu (Arm Technology China)" , "bruce.richardson@intel.com" , "thomas@monjalon.net" CC: "dev@dpdk.org" , nd , nd Thread-Topic: [dpdk-dev] [PATCH v4 2/5] meson: add infra to support machine specific flags Thread-Index: AQHUqAewqRSxhsNdjkm280sniuGqj6Xb/0kg Date: Tue, 12 Feb 2019 08:06:16 +0000 Message-ID: References: <20190106131933.7898-1-jerinj@marvell.com> <20190109103915.29210-1-pbhagavatula@marvell.com> <20190109103915.29210-2-pbhagavatula@marvell.com> In-Reply-To: <20190109103915.29210-2-pbhagavatula@marvell.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Phil.Yang@arm.com; x-originating-ip: [113.29.88.7] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DB7PR08MB3882; 20:su8jyg4LTY1+eJAMXFTWJLhkCMdcYe84QoM8GKDsC9HBeVdngrWPTM6nxzgbbitCMRyUC5G27akLfwYzk9kmEohCH+AS+eid1x8/djwQWunYkX3Xbn8AnGX+Xz9c5NXGUIBBH0BifHl02PJk3SBXSNcWYXqc3C4WnE32TKKDXhA= x-ms-office365-filtering-correlation-id: 01d8ac40-a2e1-41f4-e079-08d690c0f6fb x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB7PR08MB3882; H:DB7PR08MB3385.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: rNooutxTkCwRciLKOSlQEG9AyKjitlIDg4iwH7Fc0gw2pTi6norV/cgk15rTwLxqjproXW6QB2d4CLIWdJ8dMOZ1nyVVyEwkSTJv+lA4J/yAHeJhDGKRDTP/XUPIrsMwTIzOhbLWSjVQlz8czLwpqB4V4rV8PuByOCoF36E4dgldgQqmObfVbVDpfFu7jgEFfuGH8C6r8mPx3w4CLLZeH7kOXtjKZ15BeVlsMQnp9dewNzDYHSlBuZkuf2lD8aO0AoGuX5ZSUDEjA4mAfX/41Keoyzt/koA4MC2Uw3K123zHrdWa7Zg/y4FTb0xBULPk9XgcLoFGaCoNHI/O4AuI7CqDSfh8BwE56/dTh3st/AJgTWXodHQlQnRBYdeMGxI5/5HZWqnL2KYUYmlEWyhPn6X4fXuHV1IS8TT8L+izPlg= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 01d8ac40-a2e1-41f4-e079-08d690c0f6fb X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Feb 2019 08:06:16.9865 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR08MB3882 Subject: Re: [dpdk-dev] [PATCH v4 2/5] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Feb 2019 08:06:19 -0000 Hi Pavan, > -----Original Message----- > From: dev On Behalf Of Pavan Nikhilesh Bhagavatula > Sent: Wednesday, January 9, 2019 6:40 PM > To: jerinj@marvell.com; Gavin Hu (Arm Technology China) > ; bruce.richardson@intel.com; thomas@monjalon.net > Cc: dev@dpdk.org; Pavan Nikhilesh Bhagavatula > Subject: [dpdk-dev] [PATCH v4 2/5] meson: add infra to support machine sp= ecific > flags >=20 > From: Pavan Nikhilesh >=20 > Currently, RTE_* flags are set based on the implementer ID but there migh= t be > some micro arch specific differences from the same vendor eg. CACHE_LINES= IZE. > Add support to set micro arch specific flags. >=20 > Signed-off-by: Jerin Jacob > Signed-off-by: Pavan Nikhilesh > --- > config/arm/meson.build | 53 +++++++++++++++++++++++++----------------- > 1 file changed, 32 insertions(+), 21 deletions(-) >=20 > diff --git a/config/arm/meson.build b/config/arm/meson.build index > dae55d6b2..576363fc0 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -7,23 +7,6 @@ march_opt =3D '-march=3D@0@'.format(machine) >=20 > arm_force_native_march =3D false >=20 > -machine_args_generic =3D [ > - ['default', ['-march=3Darmv8-a+crc+crypto']], > - ['native', ['-march=3Dnative']], > - ['0xd03', ['-mcpu=3Dcortex-a53']], > - ['0xd04', ['-mcpu=3Dcortex-a35']], > - ['0xd07', ['-mcpu=3Dcortex-a57']], > - ['0xd08', ['-mcpu=3Dcortex-a72']], > - ['0xd09', ['-mcpu=3Dcortex-a73']], > - ['0xd0a', ['-mcpu=3Dcortex-a75']], > -] > -machine_args_cavium =3D [ > - ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], > - ['native', ['-march=3Dnative']], > - ['0xa1', ['-mcpu=3Dthunderxt88']], > - ['0xa2', ['-mcpu=3Dthunderxt81']], > - ['0xa3', ['-mcpu=3Dthunderxt83']]] > - > flags_common_default =3D [ > # Accelarate rte_memcpy. Be sure to run unit test > (memcpy_perf_autotest) > # to determine the best threshold in code. Refer to notes in source fil= e > @@ -50,12 +33,10 @@ flags_generic =3D [ > ['RTE_USE_C11_MEM_MODEL', true], > ['RTE_CACHE_LINE_SIZE', 128]] > flags_cavium =3D [ > - ['RTE_MACHINE', '"thunderx"'], > ['RTE_CACHE_LINE_SIZE', 128], > ['RTE_MAX_NUMA_NODES', 2], > ['RTE_MAX_LCORE', 96], > - ['RTE_MAX_VFIO_GROUPS', 128], > - ['RTE_USE_C11_MEM_MODEL', false]] > + ['RTE_MAX_VFIO_GROUPS', 128]] > flags_dpaa =3D [ > ['RTE_MACHINE', '"dpaa"'], > ['RTE_USE_C11_MEM_MODEL', true], > @@ -69,6 +50,27 @@ flags_dpaa2 =3D [ > ['RTE_MAX_NUMA_NODES', 1], > ['RTE_MAX_LCORE', 16], > ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] > +flags_default_extra =3D [] > +flags_thunderx_extra =3D [ > + ['RTE_MACHINE', '"thunderx"'], > + ['RTE_USE_C11_MEM_MODEL', false]] > + > +machine_args_generic =3D [ > + ['default', ['-march=3Darmv8-a+crc+crypto']], > + ['native', ['-march=3Dnative']], > + ['0xd03', ['-mcpu=3Dcortex-a53']], > + ['0xd04', ['-mcpu=3Dcortex-a35']], > + ['0xd07', ['-mcpu=3Dcortex-a57']], > + ['0xd08', ['-mcpu=3Dcortex-a72']], > + ['0xd09', ['-mcpu=3Dcortex-a73']], > + ['0xd0a', ['-mcpu=3Dcortex-a75']]] > + > +machine_args_cavium =3D [ > + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], > + ['native', ['-march=3Dnative']], > + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], > + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], > + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >=20 > ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) > impl_generic =3D ['Generic armv8', flags_generic, machine_args_generic] @= @ - > 157,10 +159,19 @@ else > foreach marg: machine[2] > if marg[0] =3D=3D impl_pn > foreach f: marg[1] > - machine_args +=3D f > + if cc.has_argument(f) > + machine_args +=3D f > + endif > endforeach > endif > endforeach > + > + # Apply any extra machine specific flags. > + foreach flag: marg.get(2, flags_default_extra) > + if flag.length() > 0 > + dpdk_conf.set(flag[0], flag[1]) > + endif > + endforeach I think this loop should put inside the 'if marg[0] =3D=3D impl_pn' conditi= on. The right logic should be: If marg[0] =3D=3D impl_pn # update machine_args # Apply any extra machine specific flags endif I tested this patch on thunderx2, but it set the octeontx2 extra flags into= the rte_build_config.h. Because octeontx2 is the last item of 'machine_arg= s_cavium' table. > endif > message(machine_args) >=20 > -- > 2.20.1 Thanks, Phil Yang.