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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(39850400004)(136003)(376002)(396003)(346002)(46966006)(36840700001)(316002)(356005)(82740400003)(86362001)(82310400003)(4326008)(110136005)(52536014)(336012)(33656002)(5660300002)(478600001)(36860700001)(966005)(47076005)(6506007)(83380400001)(55016002)(26005)(2906002)(7696005)(9686003)(70586007)(81166007)(186003)(8936002)(8676002)(70206006)(54906003); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2021 21:09:16.1105 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd929061-5b8a-44fc-1c44-08d913f7de96 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT015.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB6163 Subject: Re: [dpdk-dev] [EXT] Re: [PATCH] config/arm: add ability to express arch extensions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > >> > >> >05/05/2021 14:14, pbhagavatula@marvell.com: > >> >> From: Pavan Nikhilesh > >> >> > >> >> The ARM architecture allows SoCs to have extensions in addition to > >> >> base profiles such as Large System Extension (LSE), CRC etc. > >> >> > >> >> Add ability to declare SoC specific extensions. > >> >> > >> >> Signed-off-by: Pavan Nikhilesh > >> > > >> >I don't know what it is fixing. It is an optimization? > >> >Is it candidate for next release? > >> > >> Its more of an enhancement, the default n2 march flag doesn't > >describe > >> anything about the extensions that a specific SoC has. > >> In case of OCTEON 10 SoC it has support for LSE and CRC in additional > >to the > >> basic n2 profile. > >> This patch allows SoC to add extensions to the -march flag. > >> Default n2 march : -march=3Darmv8.5-a+crypto+sve2 > >> OCTEON 10 march : -march=3Darmv8.5-a+crypto+sve2+lse+crc > >> > >> Including extensions in march helps compiler generate better code. > >> Example adding '+lse' tells the compiler to inline C11 atomics rather > >than > >> having a run time jump > >> > >> https://urldefense.proofpoint.com/v2/url?u=3Dhttps- > >3A__gcc.godbolt.org_z_8hPv87dbr&d=3DDwIFAg&c=3DnKjWec2b6R0mOyPa > >z7xtfQ&r=3D1cjuAHrGh745jHNmj2fD85sUMIJ2IPIDsIJzo6FN6Z0&m=3DUs6Ig > >UW0QYnSuSc8dYw0yLXgzYvGHoBD8AKNLX0bzhw&s=3Dmk9V9_YgFBdO23 > >6JpZBIN_yhCkYAXGcE_1X315c7jGk&e=3D > >Can you compile the code with armv8.5-a instead of armv8-a? I see that > >LSE instructions are used. >=20 > Is LSE extension made mandatory from v8.1? I couldn't find a relevant > documentation on ARM website. Yes, LSE is mandatory in v8.1. You can refer to Arm-ARM document. >=20 > I have seen some compilers not in lining unless 'lse' is mentioned in mar= ch. If march provided is >=3D v8.1 the compiler should generate the LSE instruc= tions. >=20 > The patch still holds true for CRC though as it is listed separately belo= w > https://developer.arm.com/architectures/cpu-architecture/a- > profile/exploration-tools/feature-names-for-a-profile >=20 > Also, looks like sve2 support in n2 core might be optional as per above d= oc? I need to check on this. Some of the info here might not be public yet. >=20 > >https://urldefense.proofpoint.com/v2/url?u=3Dhttps- > >3A__gcc.godbolt.org_z_18MYhY7xv&d=3DDwIFAg&c=3DnKjWec2b6R0mOyP > >az7xtfQ&r=3D1cjuAHrGh745jHNmj2fD85sUMIJ2IPIDsIJzo6FN6Z0&m=3DUs6I > >gUW0QYnSuSc8dYw0yLXgzYvGHoBD8AKNLX0bzhw&s=3DIpCFzI_hPuBl0P6 > >Ylbrfm-1WXvdGg9mwnuzpwC6PrCM&e=3D > > > >> > >> I don't think this is limited to OCTEON 10 other SoC should also add > >their > >> extensions to march. > >> > >> > > >> >> --- > >> >> > >> >> More details about ARM extensions > >> >> https://urldefense.proofpoint.com/v2/url?u=3Dhttps- > >> > >>3A__developer.arm.com_documentation_102378_0200&d=3DDwICAg& > >c > >> > >>=3DnKjWec2b6R0mOyPaz7xtfQ&r=3D1cjuAHrGh745jHNmj2fD85sUMIJ2IPID > >s > >> > >>IJzo6FN6Z0&m=3DyCt4te5_7VJvaJT5OXrOpFXH3UBOUqRDlHZuSVEUZH > >M > >> >&s=3DDquFBMwxMpjxWcM2Qw1c2t_ak-j6DN4rz8ce_I43RJk&e=3D > >> >> > >> >> config/arm/meson.build | 8 ++++++++ > >> >> 1 file changed, 8 insertions(+) > >> >> > >> >> diff --git a/config/arm/meson.build b/config/arm/meson.build > >index > >> >> 22cd81319..8aa961e5b 100644 > >> >> --- a/config/arm/meson.build > >> >> +++ b/config/arm/meson.build > >> >> @@ -230,6 +230,7 @@ soc_cn10k =3D { > >> >> ['RTE_MAX_LCORE', 24], > >> >> ['RTE_MAX_NUMA_NODES', 1] > >> >> ], > >> >> + 'extensions' : ['lse', 'crc'], > >> >> 'part_number': '0xd49', > >> >> 'numa': false > >> >> } > >> >> @@ -387,6 +388,7 @@ else > >> >> endif > >> >> > >> >> soc_flags =3D [] > >> >> + soc_extensions =3D [] > >> >> if soc_config.has_key('not_supported') > >> >> error('SoC @0@ not supported.'.format(soc)) > >> >> elif soc_config !=3D {} > >> >> @@ -394,6 +396,7 @@ else > >> >> implementer_config =3D implementers[implementer_id] > >> >> part_number =3D soc_config['part_number'] > >> >> soc_flags =3D soc_config.get('flags', []) > >> >> + soc_extensions =3D soc_config.get('extensions', []) > >> >> if not soc_config.get('numa', true) > >> >> has_libnuma =3D 0 > >> >> endif > >> >> @@ -431,6 +434,11 @@ else > >> >> # apply supported machine args > >> >> machine_args =3D [] # Clear previous machine args > >> >> foreach flag: part_number_config['machine_args'] > >> >> + if flag.startswith('-march') and soc_extensions.length() > >> >> + !=3D > >> >> + 0 > >> > > >> >Why condition on start with -march? > >> > >> There are some implementer flags which don't have -march to add > >extensions > >> to. > >> > >> > > >> >> + foreach ex: soc_extensions > >> >> + flag +=3D '+' + ex > >> >> + endforeach > >> >> + endif > >> > > >> >