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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(396003)(346002)(39860400002)(136003)(376002)(36840700001)(46966006)(7696005)(36860700001)(478600001)(450100002)(33656002)(81166007)(9686003)(5660300002)(70586007)(70206006)(8936002)(356005)(55016002)(54906003)(316002)(52536014)(83380400001)(336012)(186003)(26005)(86362001)(47076005)(8676002)(82740400003)(2906002)(6506007)(82310400003)(110136005)(4326008); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 18:06:47.3014 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9bc02d7-aec9-46fa-7607-08d977aa6b02 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT051.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3PR08MB5755 Subject: Re: [dpdk-dev] [PATCH 2/2] net/i40e: fix risk in Rx descriptor read in scalar path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >=20 > Rx descriptor is 16B/32B in size and consists of multiple words. > The word that includes DD field should be read first. Read result with DD= bit > set indicates the rest part in a descriptor is valid. Suggest rewording as follows: Rx descriptor is 16B/32B in size. If the DD bit is set, it indicates that t= he rest of the descriptor words have valid values. Hence, the word containi= ng DD bit must be read first before reading the rest of the descriptor word= s. >=20 > In functions for simple Rx, the descriptor is not read atomically in whol= e. On > weaker ordered systems like aarch64, read of the word that includes DD fi= eld > could be reordered after read of other words. > In this case, some words could be invalid data. Since the entire descriptor is not read atomically, on relaxed memory order= ed systems like Aarch64, read of the word containing DD field could be reor= dered after read of other words. >=20 > Read barrier is inserted between read of the word with DD field and read = of > other words. The barrier ensures what fetched is correct descriptor data. Suggest capturing the performance impact, so it is clearly documented. >=20 > Fixes: 7b0cf70135d1 ("net/i40e: support ARM platform") > Cc: stable@dpdk.org >=20 > Signed-off-by: Ruifeng Wang With the above comments, Reviewed-by: Honnappa Nagarahalli > --- > The change should not impact performance on x86 as acquire fence is ignor= ed > on x86. >=20 > drivers/net/i40e/i40e_rxtx.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) >=20 > diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c = index > 8329cbdd4e..c4cd6b6b60 100644 > --- a/drivers/net/i40e/i40e_rxtx.c > +++ b/drivers/net/i40e/i40e_rxtx.c > @@ -746,6 +746,12 @@ i40e_recv_pkts(void *rx_queue, struct rte_mbuf > **rx_pkts, uint16_t nb_pkts) > break; > } >=20 > + /** > + * Use acquire fence to ensure that qword1 which includes DD > + * bit is loaded before loading of other descriptor words. > + */ > + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); > + > rxd =3D *rxdp; > nb_hold++; > rxe =3D &sw_ring[rx_id]; > @@ -862,6 +868,12 @@ i40e_recv_scattered_pkts(void *rx_queue, > break; > } >=20 > + /** > + * Use acquire fence to ensure that qword1 which includes DD > + * bit is loaded before loading of other descriptor words. > + */ > + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); > + > rxd =3D *rxdp; > nb_hold++; > rxe =3D &sw_ring[rx_id]; > -- > 2.25.1