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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(52536014)(316002)(6506007)(81166007)(110136005)(54906003)(7696005)(336012)(5660300002)(356005)(55016002)(70206006)(86362001)(26005)(186003)(70586007)(2906002)(36860700001)(47076005)(82310400003)(508600001)(83380400001)(4326008)(450100002)(9686003)(33656002)(8676002)(8936002); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 18:33:36.7103 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b5eb24bf-00b9-4518-5996-08d977ae2a56 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT037.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB2783 Subject: Re: [dpdk-dev] [PATCH 1/2] net/i40e: fix risk in Rx descriptor read in NEON vector path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Similar comments that I have to patch 2/2 >=20 > Rx descriptor is 16B/32B in size and consists of multiple words. > The word that includes DD field should be read first. Read result with DD= bit > set indicates the rest part in a descriptor is valid. Suggest rewording as follows: Rx descriptor is 16B/32B in size. If the DD bit is set, it indicates that t= he rest of the descriptor words have valid values. Hence, the word containi= ng DD bit must be read first before reading the rest of the descriptor word= s. >=20 > In NEON vector PMD, vector load loads two contiguous 8B of descriptor dat= a > into vector register. Given vector load ensures no 16B atomicity, read of= the > word that includes DD field could be reordered after read of other words.= In > this case, some words could be invalid data. "some words could contain invalid data" >=20 > Read barrier is added after read of qword1 that includes DD field. > And qword0 is reloaded to update vector register. This ensures what fetch= ed > is correct descriptor data. "This ensures that the fetched data is correct". Suggest capturing the performance impact, so it is clearly documented. >=20 > Fixes: ae0eb310f253 ("net/i40e: implement vector PMD for ARM") > Cc: stable@dpdk.org >=20 > Signed-off-by: Ruifeng Wang With the above comments, Reviewed-by: Honnappa Nagarahalli > --- > drivers/net/i40e/i40e_rxtx_vec_neon.c | 8 ++++++++ > 1 file changed, 8 insertions(+) >=20 > diff --git a/drivers/net/i40e/i40e_rxtx_vec_neon.c > b/drivers/net/i40e/i40e_rxtx_vec_neon.c > index b2683fda60..71191c7cc8 100644 > --- a/drivers/net/i40e/i40e_rxtx_vec_neon.c > +++ b/drivers/net/i40e/i40e_rxtx_vec_neon.c > @@ -286,6 +286,14 @@ _recv_raw_pkts_vec(struct i40e_rx_queue > *__rte_restrict rxq, > descs[1] =3D vld1q_u64((uint64_t *)(rxdp + 1)); > descs[0] =3D vld1q_u64((uint64_t *)(rxdp)); >=20 > + /* Use acquire fence to order loads of descriptor qwords */ > + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); > + /* A.2 reload qword0 to make it ordered after qword1 load */ > + descs[3] =3D vld1q_lane_u64((uint64_t *)(rxdp + 3), descs[3], > 0); > + descs[2] =3D vld1q_lane_u64((uint64_t *)(rxdp + 2), descs[2], > 0); > + descs[1] =3D vld1q_lane_u64((uint64_t *)(rxdp + 1), descs[1], > 0); > + descs[0] =3D vld1q_lane_u64((uint64_t *)(rxdp), descs[0], 0); > + > /* B.1 load 4 mbuf point */ > mbp1 =3D vld1q_u64((uint64_t *)&sw_ring[pos]); > mbp2 =3D vld1q_u64((uint64_t *)&sw_ring[pos + 2]); > -- > 2.25.1