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Wed, 12 May 2021 23:21:38 +0000 Received: from DBAPR08MB5814.eurprd08.prod.outlook.com ([fe80::f15f:821c:74c5:2482]) by DBAPR08MB5814.eurprd08.prod.outlook.com ([fe80::f15f:821c:74c5:2482%2]) with mapi id 15.20.4129.025; Wed, 12 May 2021 23:21:38 +0000 From: Honnappa Nagarahalli To: Chengwen Feng , "thomas@monjalon.net" , "ferruh.yigit@intel.com" CC: "dev@dpdk.org" , "jerinj@marvell.com" , Ruifeng Wang , "viktorin@rehivetech.com" , "bruce.richardson@intel.com" , nd , Honnappa Nagarahalli , nd Thread-Topic: [PATCH 2/2] net/hns3: refactor SVE code compile method Thread-Index: AQHXRwlKc4fxsI0SS0KXXIdURovZZ6rgePlAgAADZcA= Date: Wed, 12 May 2021 23:21:37 +0000 Message-ID: References: <1620808126-18876-1-git-send-email-fengchengwen@huawei.com> <1620808126-18876-3-git-send-email-fengchengwen@huawei.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ts-tracking-id: D1F4E906441120489B95EDC63F3BE005.0 x-checkrecipientchecked: true Authentication-Results-Original: huawei.com; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(136003)(376002)(39860400002)(346002)(396003)(36840700001)(46966006)(82310400003)(52536014)(356005)(81166007)(47076005)(110136005)(2906002)(36860700001)(82740400003)(7696005)(54906003)(4326008)(33656002)(6506007)(8676002)(83380400001)(86362001)(2940100002)(26005)(9686003)(336012)(5660300002)(70206006)(316002)(966005)(8936002)(478600001)(55016002)(70586007)(186003); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2021 23:21:44.7055 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 972334ff-1442-4ce7-488b-08d9159cb51a X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT020.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0802MB2415 Subject: Re: [dpdk-dev] [PATCH 2/2] net/hns3: refactor SVE code compile method X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >=20 > > > > Currently, the SVE code is compiled only when -march supports SVE > > (e.g. '- march=3Darmv8.2a+sve'), there maybe some problem[1] with this > approach. > > > > The solution: > > a. If the minimum instruction set support SVE then compiles it. > > b. Else if the compiler support SVE then compiles it. > > c. Otherwise don't compile it. > > > > [1] https://mails.dpdk.org/archives/dev/2021-April/208189.html > > > > Fixes: 8c25b02b082a ("net/hns3: fix enabling SVE Rx/Tx") > > Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") > > Cc: stable@dpdk.org > > > > Signed-off-by: Chengwen Feng > > --- > > drivers/net/hns3/hns3_rxtx.c | 2 +- > > drivers/net/hns3/meson.build | 13 +++++++++++++ > > 2 files changed, 14 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/net/hns3/hns3_rxtx.c > > b/drivers/net/hns3/hns3_rxtx.c index > > 1d7a769..4ef20c6 100644 > > --- a/drivers/net/hns3/hns3_rxtx.c > > +++ b/drivers/net/hns3/hns3_rxtx.c > > @@ -2808,7 +2808,7 @@ hns3_get_default_vec_support(void) > > static bool > > hns3_get_sve_support(void) > > { > > -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) > > +#if defined(CC_SVE_SUPPORT) > > if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) > > return false; > > if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) > > diff --git a/drivers/net/hns3/meson.build > > b/drivers/net/hns3/meson.build index > > 53c7df7..8563d70 100644 > > --- a/drivers/net/hns3/meson.build > > +++ b/drivers/net/hns3/meson.build > > @@ -35,7 +35,20 @@ deps +=3D ['hash'] > > > > if arch_subdir =3D=3D 'arm' and dpdk_conf.get('RTE_ARCH_64') > > sources +=3D files('hns3_rxtx_vec.c') > > + > > + # compile SVE when: > > + # a. support SVE in minimum instruction set baseline > > + # b. it's not minimum instruction set, but compiler support > > if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) !=3D '' > > + cflags +=3D ['-DCC_SVE_SUPPORT'] > Why is the CC_SVE_SUPPORT flag needed? The compiler has > __ARM_FEATURE_SVE flag already which gets defined when '+sve" is added to > '-march'. >=20 > > sources +=3D files('hns3_rxtx_vec_sve.c') > > + elif cc.has_argument('-march=3Darmv8.2-a+sve') > I think this check and the above check do the same thing. i.e. both of th= em > check if +sve flag is passed to the compiler. >=20 > > + cflags +=3D ['-DCC_SVE_SUPPORT'] > > + hns3_sve_lib =3D static_library('hns3_sve_lib', > > + 'hns3_rxtx_vec_sve.c', > > + dependencies: [static_rte_ethdev], > > + include_directories: includes, > > + c_args: [cflags, '-march=3Darmv8.2-a+sve']) > > + objs +=3D hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c') I do not understand the need of this block of code, appreciate if you could= explain why this is required. > > endif > > endif > > -- > > 2.8.1