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Wed, 8 Apr 2020 21:16:14 +0000 Received: from DBBPR08MB4646.eurprd08.prod.outlook.com ([fe80::1870:afc4:b90f:609d]) by DBBPR08MB4646.eurprd08.prod.outlook.com ([fe80::1870:afc4:b90f:609d%5]) with mapi id 15.20.2878.021; Wed, 8 Apr 2020 21:16:14 +0000 From: Honnappa Nagarahalli To: "Carrillo, Erik G" , Phil Yang , "rsanford@akamai.com" , "dev@dpdk.org" CC: "david.marchand@redhat.com" , "Burakov, Anatoly" , "thomas@monjalon.net" , "jerinj@marvell.com" , "hemant.agrawal@nxp.com" , Gavin Hu , nd , Honnappa Nagarahalli , nd Thread-Topic: [PATCH 2/2] lib/timer: relax barrier for status update Thread-Index: AQHWDeodFNsTow5NnU2kr/yq0gxiTahvuM1g Date: Wed, 8 Apr 2020 21:16:13 +0000 Message-ID: References: <1582526539-14360-1-git-send-email-phil.yang@arm.com> <1582526539-14360-2-git-send-email-phil.yang@arm.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ts-tracking-id: 9c639d61-0daf-4af0-b83c-1bab6c50d204.0 x-checkrecipientchecked: true Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Honnappa.Nagarahalli@arm.com; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB2946 Subject: Re: [dpdk-dev] [PATCH 2/2] lib/timer: relax barrier for status update X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > > Subject: [PATCH 2/2] lib/timer: relax barrier for status update > > > > Volatile has no ordering semantics. The rte_timer structure defines > > timer status as a volatile variable and uses the rte_r/wmb barrier to > > guarantee inter-thread visibility. > > > > This patch optimized the volatile operation with c11 atomic operations > > and one-way barrier to save the performance penalty. According to the > > timer_perf_autotest benchmarking results, this patch can uplift > > 10%~16% timer appending performance, 3%~20% timer resetting > > performance and 45% timer callbacks scheduling performance on aarch64 > > and no loss in performance for x86. > > > > Suggested-by: Honnappa Nagarahalli > > Signed-off-by: Phil Yang > > Reviewed-by: Gavin Hu >=20 > Hi Phil, >=20 > It seems like the consensus is to generally avoid replacing rte_atomic_* > interfaces with the GCC builtins directly. In other areas of DPDK that = are > being patched, are the C11 APIs going to be investigated? = It > seems like that decision will apply here as well. Agree. The new APIs are going to be 1 to 1 mapped with the built-in intrins= ics (the memory orderings used themselves will not change). We should go ah= ead with the review and conclude any issues. Once the decision is made on w= hat APIs to use, we can submit the next version using the APIs decided. >=20 > Thanks, > Erik >=20 > > --- > > lib/librte_timer/rte_timer.c | 90 +++++++++++++++++++++++++++++++---- > > --------- > > lib/librte_timer/rte_timer.h | 2 +- > > 2 files changed, 65 insertions(+), 27 deletions(-) > > > > diff --git a/lib/librte_timer/rte_timer.c > > b/lib/librte_timer/rte_timer.c index 269e921..be0262d 100644 > > --- a/lib/librte_timer/rte_timer.c > > +++ b/lib/librte_timer/rte_timer.c > > @@ -10,7 +10,6 @@ > > #include > > #include > > > > -#include > > #include > > #include > > #include > > @@ -218,7 +217,7 @@ rte_timer_init(struct rte_timer *tim) > > > > status.state =3D RTE_TIMER_STOP; > > status.owner =3D RTE_TIMER_NO_OWNER; > > - tim->status.u32 =3D status.u32; > > + __atomic_store_n(&tim->status.u32, status.u32, > > __ATOMIC_RELAXED); > > } > > > > /* > > @@ -239,9 +238,9 @@ timer_set_config_state(struct rte_timer *tim, > > > > /* wait that the timer is in correct status before update, > > * and mark it as being configured */ > > - while (success =3D=3D 0) { > > - prev_status.u32 =3D tim->status.u32; > > + prev_status.u32 =3D __atomic_load_n(&tim->status.u32, > > __ATOMIC_RELAXED); > > > > + while (success =3D=3D 0) { > > /* timer is running on another core > > * or ready to run on local core, exit > > */ > > @@ -258,9 +257,20 @@ timer_set_config_state(struct rte_timer *tim, > > * mark it atomically as being configured */ > > status.state =3D RTE_TIMER_CONFIG; > > status.owner =3D (int16_t)lcore_id; > > - success =3D rte_atomic32_cmpset(&tim->status.u32, > > - prev_status.u32, > > - status.u32); > > + /* If status is observed as RTE_TIMER_CONFIG earlier, > > + * that's not going to cause any issues because the > > + * pattern is read for status then read the other members. > > + * In one of the callers to timer_set_config_state > > + * (the __rte_timer_reset) we set other members to the > > + * structure (period, expire, f, arg) we want these > > + * changes to be observed after our change to status. > > + * So we need __ATOMIC_ACQUIRE here. > > + */ > > + success =3D __atomic_compare_exchange_n(&tim- > > >status.u32, > > + &prev_status.u32, > > + status.u32, 0, > > + __ATOMIC_ACQUIRE, > > + __ATOMIC_RELAXED); > > } > > > > ret_prev_status->u32 =3D prev_status.u32; @@ -279,20 +289,27 @@ > > timer_set_running_state(struct rte_timer *tim) > > > > /* wait that the timer is in correct status before update, > > * and mark it as running */ > > - while (success =3D=3D 0) { > > - prev_status.u32 =3D tim->status.u32; > > + prev_status.u32 =3D __atomic_load_n(&tim->status.u32, > > __ATOMIC_RELAXED); > > > > + while (success =3D=3D 0) { > > /* timer is not pending anymore */ > > if (prev_status.state !=3D RTE_TIMER_PENDING) > > return -1; > > > > /* here, we know that timer is stopped or pending, > > - * mark it atomically as being configured */ > > + * mark it atomically as being running > > + */ > > status.state =3D RTE_TIMER_RUNNING; > > status.owner =3D (int16_t)lcore_id; > > - success =3D rte_atomic32_cmpset(&tim->status.u32, > > - prev_status.u32, > > - status.u32); > > + /* RUNNING states are acting as locked states. If the > > + * timer is in RUNNING state, the state cannot be changed > > + * by other threads. So, we should use ACQUIRE here. > > + */ > > + success =3D __atomic_compare_exchange_n(&tim- > > >status.u32, > > + &prev_status.u32, > > + status.u32, 0, > > + __ATOMIC_ACQUIRE, > > + __ATOMIC_RELAXED); > > } > > > > return 0; > > @@ -520,10 +537,12 @@ __rte_timer_reset(struct rte_timer *tim, > > uint64_t expire, > > > > /* update state: as we are in CONFIG state, only us can modify > > * the state so we don't need to use cmpset() here */ > > - rte_wmb(); > > status.state =3D RTE_TIMER_PENDING; > > status.owner =3D (int16_t)tim_lcore; > > - tim->status.u32 =3D status.u32; > > + /* The "RELEASE" ordering guarantees the memory operations above > > + * the status update are observed before the update by all threads > > + */ > > + __atomic_store_n(&tim->status.u32, status.u32, > > __ATOMIC_RELEASE); > > > > if (tim_lcore !=3D lcore_id || !local_is_locked) > > rte_spinlock_unlock(&priv_timer[tim_lcore].list_lock); > > @@ -600,10 +619,12 @@ __rte_timer_stop(struct rte_timer *tim, int > > local_is_locked, > > } > > > > /* mark timer as stopped */ > > - rte_wmb(); > > status.state =3D RTE_TIMER_STOP; > > status.owner =3D RTE_TIMER_NO_OWNER; > > - tim->status.u32 =3D status.u32; > > + /* The "RELEASE" ordering guarantees the memory operations above > > + * the status update are observed before the update by all threads > > + */ > > + __atomic_store_n(&tim->status.u32, status.u32, > > __ATOMIC_RELEASE); > > > > return 0; > > } > > @@ -637,7 +658,8 @@ rte_timer_stop_sync(struct rte_timer *tim) int > > rte_timer_pending(struct rte_timer *tim) { > > - return tim->status.state =3D=3D RTE_TIMER_PENDING; > > + return __atomic_load_n(&tim->status.state, > > + __ATOMIC_RELAXED) =3D=3D > > RTE_TIMER_PENDING; > > } > > > > /* must be called periodically, run all timer that expired */ @@ > > -739,8 > > +761,12 @@ __rte_timer_manage(struct rte_timer_data *timer_data) > > /* remove from done list and mark timer as stopped > */ > > status.state =3D RTE_TIMER_STOP; > > status.owner =3D RTE_TIMER_NO_OWNER; > > - rte_wmb(); > > - tim->status.u32 =3D status.u32; > > + /* The "RELEASE" ordering guarantees the memory > > + * operations above the status update are observed > > + * before the update by all threads > > + */ > > + __atomic_store_n(&tim->status.u32, status.u32, > > + __ATOMIC_RELEASE); > > } > > else { > > /* keep it in list and mark timer as pending */ @@ - > > 748,8 +774,12 @@ __rte_timer_manage(struct rte_timer_data *timer_data) > > status.state =3D RTE_TIMER_PENDING; > > __TIMER_STAT_ADD(priv_timer, pending, 1); > > status.owner =3D (int16_t)lcore_id; > > - rte_wmb(); > > - tim->status.u32 =3D status.u32; > > + /* The "RELEASE" ordering guarantees the memory > > + * operations above the status update are observed > > + * before the update by all threads > > + */ > > + __atomic_store_n(&tim->status.u32, status.u32, > > + __ATOMIC_RELEASE); > > __rte_timer_reset(tim, tim->expire + tim->period, > > tim->period, lcore_id, tim->f, tim->arg, 1, > > timer_data); > > @@ -919,8 +949,12 @@ rte_timer_alt_manage(uint32_t timer_data_id, > > /* remove from done list and mark timer as stopped > */ > > status.state =3D RTE_TIMER_STOP; > > status.owner =3D RTE_TIMER_NO_OWNER; > > - rte_wmb(); > > - tim->status.u32 =3D status.u32; > > + /* The "RELEASE" ordering guarantees the memory > > + * operations above the status update are observed > > + * before the update by all threads > > + */ > > + __atomic_store_n(&tim->status.u32, status.u32, > > + __ATOMIC_RELEASE); > > } else { > > /* keep it in list and mark timer as pending */ > > rte_spinlock_lock( > > @@ -928,8 +962,12 @@ rte_timer_alt_manage(uint32_t timer_data_id, > > status.state =3D RTE_TIMER_PENDING; > > __TIMER_STAT_ADD(data->priv_timer, pending, 1); > > status.owner =3D (int16_t)this_lcore; > > - rte_wmb(); > > - tim->status.u32 =3D status.u32; > > + /* The "RELEASE" ordering guarantees the memory > > + * operations above the status update are observed > > + * before the update by all threads > > + */ > > + __atomic_store_n(&tim->status.u32, status.u32, > > + __ATOMIC_RELEASE); > > __rte_timer_reset(tim, tim->expire + tim->period, > > tim->period, this_lcore, tim->f, tim->arg, 1, > > data); > > diff --git a/lib/librte_timer/rte_timer.h > > b/lib/librte_timer/rte_timer.h index c6b3d45..df533fa 100644 > > --- a/lib/librte_timer/rte_timer.h > > +++ b/lib/librte_timer/rte_timer.h > > @@ -101,7 +101,7 @@ struct rte_timer > > { > > uint64_t expire; /**< Time when timer expire. */ > > struct rte_timer *sl_next[MAX_SKIPLIST_DEPTH]; > > - volatile union rte_timer_status status; /**< Status of timer. */ > > + union rte_timer_status status; /**< Status of timer. */ > > uint64_t period; /**< Period of timer (0 if not periodic). */ > > rte_timer_cb_t f; /**< Callback function. */ > > void *arg; /**< Argument to callback function. */ > > -- > > 2.7.4